Distinguished Technologist - AI Model Performance Architect

HP
Texas, Palo Alto
Workplace: OnsiteFull timeUSD 190,000 - 274,000 annuallyFunction: Hardware, Embedded & Systems EngineeringExperience: 12+ yearsEducation: bachelorsSkills: ["Effective communication","Results orientation","Learning agility","Digital fluency","Customer centricity"]

Bridge system memory architecture with AI model behavior to improve performance via HW/SW co-design and workload-aware tuning. Develop AI workload optimization strategies to reduce startup time, enhance inferencing efficiency, and minimize memory needs. Analyze bandwidth/latency bottlenecks, model performance across CPU/GPU/NPU, and simulate/optimize execution details like initialization, caching, and KV reuse. Lead R&D, influence long-term roadmaps, and partner across ML and hardware engineering teams.

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FursaFursa
HP
HP
3 months ago

Distinguished Technologist - AI Model Performance Architect

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Source: Company careers pageValidated by: Fursa AI
Last checked: 6 hours agoStatus: Live
Reposted: similar role first listed 1 month ago

Job Summary

Bridge system memory architecture with AI model behavior to improve performance via HW/SW co-design and workload-aware tuning. Develop AI workload optimization strategies to reduce startup time, enhance inferencing efficiency, and minimize memory needs. Analyze bandwidth/latency bottlenecks, model performance across CPU/GPU/NPU, and simulate/optimize execution details like initialization, caching, and KV reuse. Lead R&D, influence long-term roadmaps, and partner across ML and hardware engineering teams.
Location: Texas, Palo Alto
Workplace: Onsite
Employment Type: Full time
Job Function: Hardware, Embedded & Systems Engineering
Seniority: Mid level

Key Responsibilities

  • •Analyze system bandwidth, latency, and compute bottlenecks for AI workloads.
  • •Model and evaluate AI performance across CPU/GPU/NPU.
  • •Simulate workload execution and address PnP tradeoffs and resource contention.
  • •Optimize model execution, including initialization time, caching, and KV reuse.
  • •Drive HW/SW co-design and partner with ML teams to align model structure with system architecture, while leading technology roadmaps and R&D.

Pay and Benefits

Salary: USD 190,000 - 274,000 annually
Perks:Health InsuranceDentalVisionDisability InsuranceLife InsurancePaid HolidaysParental Leave

Key Requirements

  • •Four-year or Graduate Degree in Electrical Engineering or a related discipline, or commensurate work experience demonstrating competence.
  • •Typically 12+ years of work experience in electrical design/tools, software packages, electronic hardware architecture, or a related field.
  • •Expertise in memory and AI model design, with strong system and hardware architecture understanding.
  • •Ability to analyze system bandwidth, latency, and compute bottlenecks for AI workloads.
  • •Experience driving HW/SW co-design and aligning model structure with system architecture in partnership with ML teams.
Experience:12+ years
Education:Bachelor's in Electrical Engineering
Skills:Effective communicationResults orientationLearning agilityDigital fluencyCustomer centricity
Tech Stack:CPUGPUNPUField-Programmable Gate Array (FPGA)MATLABOscilloscopePrinted Circuit BoardSchematic CaptureSimulationsSystems DesignHardware ArchitectureHardware Design

Company Brief

HP
Designs and manufactures personal computers, printers, and related supplies, as well as provides software, services, and solutions for consumers and enterprises worldwide.
Industry: Hardware Devices
Company Size: Enterprise (1,001+ employees)
Revenue: USD 1B+
Growth: Public Company
Valuation: Public Company (Market Cap in USD)
Funding: IPO / Publicly Listed
Headquarters: Palo Alto, United States
Founded: 1939
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