Staff SoC DFT Engineer, HBM

Micron Technology
United States
Workplace: OnsiteFull timeFunction: Hardware, Embedded & Systems EngineeringEducation: bachelorsSkills: ["Communication","Collaboration","Problem-solving","Mentoring","Cross-functional teamwork"]

Own design-for-test (DFT) architecture and implementation for complex high-bandwidth memory (HBM) system-on-chip (SoC) base-die designs. Drive DFT planning early, integrate scan, MBIST/LBIST, and JTAG access, and execute DFT flows through linting, CDC checks, rule checks, ATPG readiness, and coverage closure. Partner across RTL-to-GDS teams to optimize DFT for physical design and support pre- and post-silicon debug and bring-up.

Loading

Loading job details...

Preparing the role view and application actions.

FursaFursa
Micron Technology
Micron Technology
2 months ago

Staff SoC DFT Engineer, HBM

✓ Verified Job

Canonical indexed version, validated from employer's careers page.

Source: Company careers pageValidated by: Fursa AI
Last checked: 18 hours agoStatus: Live

Job Summary

Own design-for-test (DFT) architecture and implementation for complex high-bandwidth memory (HBM) system-on-chip (SoC) base-die designs. Drive DFT planning early, integrate scan, MBIST/LBIST, and JTAG access, and execute DFT flows through linting, CDC checks, rule checks, ATPG readiness, and coverage closure. Partner across RTL-to-GDS teams to optimize DFT for physical design and support pre- and post-silicon debug and bring-up.
Location: United States
Workplace: Onsite
Employment Type: Full time
Job Function: Hardware, Embedded & Systems Engineering
Seniority: Sr. Manager level

Key Responsibilities

  • •Own SoC-level DFT architecture and implementation for scan, MBIST/LBIST, boundary scan (JTAG), and test access for HBM base-die designs.
  • •Define and drive DFT architecture early, aligning with SoC integration, floorplanning, timing, power, and physical design requirements.
  • •Implement and integrate DFT logic across block, subsystem, and full-chip levels with RTL design and SoC integration teams.
  • •Execute DFT flows including linting, CDC checks, DFT rule checks, ATPG readiness, and coverage closure with signoff.
  • •Collaborate with verification, product engineering, test, probe, and manufacturing teams to ensure testability and support silicon bring-up and debug.

Pay and Benefits

Perks:MedicalDentalVisionPaid LeavePaid HolidaysParental LeaveIncome Protection

Key Requirements

  • •Strong hands-on experience with SoC design for test (DFT), including scan insertion, MBIST/LBIST, boundary scan (JTAG), and ATPG.
  • •Experience across full RTL-to-GDS SoC flows and collaboration with synthesis, static timing analysis (STA), and physical design teams.
  • •Proficiency using EDA tools from Siemens, Synopsys, and/or Cadence for DFT and implementation.
  • •Bachelor’s degree in Electrical Engineering, Computer Engineering, or a related field, or equivalent practical experience.
  • •Seven or more years of relevant experience in SoC design, DFT, or implementation for complex digital ASICs or SoCs.
Experience:SemiconductorsSoCASICMemory systemsHBM
Education:Bachelor's in Electrical Engineering, Computer Engineering, or a related field
Skills:CommunicationCollaborationProblem-solvingMentoringCross-functional teamwork
Tech Stack:DFTScan insertionMBISTLBISTJTAGATPGRTLGDSSTAEDASiemens EDASynopsysCadenceLintingCDC checksCoverage closurePythonTclPerlDRC

Company Brief

Micron Technology
Designs and manufactures semiconductor memory and storage solutions, including DRAM, NAND, and NOR flash, for computing, networking, mobile, and automotive markets worldwide.
Industry: Electronics Manufacturing
Company Size: Enterprise (1,001+ employees)
Revenue: USD 1B+
Growth: Public Company
Valuation: Public Company (Market Cap in USD)
Funding: IPO / Publicly Listed
Headquarters: Boise, United States
Founded: 1978
Glassdoor
Glassdoor: 3.7
WebsiteLinkedIn