Senior Physical Design Engineer

AMD
Santa Clara
Workplace: HybridFull timeUSD 184,100 - 315,600 annuallyFunction: Design (Product/UX/UI/Visual)Education: bachelorsSkills: ["Technical leadership","Mentorship","Cross-functional collaboration","Analytical thinking","Troubleshooting"]

Lead advanced-node physical design for complex ASIC and SoC products, driving implementation, timing closure, signoff readiness, and PPA optimization from block through chip level. Partner with architecture, RTL, CAD, technology, and product engineering teams to deliver high-quality silicon while enhancing methodologies, automation, and data-driven workflows. Perform timing and variation-aware analysis, clock-tree optimization, ECO strategy execution, and support verification and tapeout preparation.

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FursaFursa
AMD
AMD
1 day ago

Senior Physical Design Engineer

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Last checked: 9 hours agoStatus: Live

Job Summary

Lead advanced-node physical design for complex ASIC and SoC products, driving implementation, timing closure, signoff readiness, and PPA optimization from block through chip level. Partner with architecture, RTL, CAD, technology, and product engineering teams to deliver high-quality silicon while enhancing methodologies, automation, and data-driven workflows. Perform timing and variation-aware analysis, clock-tree optimization, ECO strategy execution, and support verification and tapeout preparation.
Location: Santa Clara
Workplace: Hybrid
Employment Type: Full time
Job Function: Design (Product/UX/UI/Visual)
Seniority: Mid level

Key Responsibilities

  • •Lead physical design activities across block, subsystem, and chip-level implementations.
  • •Drive timing closure, signoff readiness, and PPA optimization for advanced-node designs.
  • •Develop and enhance physical design methodologies, design flows, and automation solutions.
  • •Perform static and variation-aware timing analysis and execute clock-tree optimization.
  • •Define and execute ECO strategies; support verification and tapeout preparation while analyzing design data and trends.

Pay and Benefits

Salary: USD 184,100 - 315,600 annually

Key Requirements

  • •Experience with ASIC physical design, implementation, and timing closure.
  • •Strong knowledge of static timing analysis, clock-tree synthesis, signoff, and ECO methodologies.
  • •Hands-on experience across block, subsystem, and chip-level design environments.
  • •Proficiency with industry tools such as Synopsys ICC2, Fusion Compiler, and/or Cadence Innovus.
  • •Strong scripting and automation skills (e.g., TCL, Python, Perl, Pandas) and experience with design flows/methodologies.
Experience:ASIC physical designSemiconductor designAdvanced-node
Education:Bachelor's in Electrical Engineering, Computer Engineering, Computer Science, or a related technical field
Skills:Technical leadershipMentorshipCross-functional collaborationAnalytical thinkingTroubleshooting
Languages:En-us
Tech Stack:ASICSoCRTLCADSynopsys ICC2Fusion CompilerCadence InnovusPrimeTimePrimeTime PXPrimeShieldRedHawkFormalityConformalStatic timing analysisClock-tree optimizationECOTCLPythonPerlPandas

Eligibility

Work Authorization:Authorization required. Sponsorship not provided.

Company Brief

AMD
Designs and produces semiconductor products including CPUs, GPUs, and adaptive SoCs for consumer, enterprise, and embedded markets, competing across PCs, data centers, and gaming industries.
Industry: Electronics Manufacturing
Company Size: Enterprise (1,001+ employees)
Revenue: USD 1B+
Growth: Public Company
Valuation: Public Company (Market Cap in USD)
Funding: IPO / Publicly Listed
Headquarters: Santa Clara, United States
Founded: 1969
Glassdoor
Glassdoor: 3.9
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