Texas Instruments

Recent

Design Verification Engineer

✓ Verified Job

Canonical indexed version, validated from employer's careers page.

Source: Company careers pageValidated by: Fursa AI

Last checked: 13 hours agoStatus: Live

Job Summary

Confirm the accuracy of analog and mixed-signal designs by validating IP/subsystem/SoC requirements from spec definition through post-silicon verification. Own the verification strategy, environment (TB, checkers, coverage monitors, DV flow updates), and run functional/firmware verification across RTL/PARTL and GLS/PAGLS modes. Collaborate with architecture, RTL, DFT, systems, analog, firmware, and application teams, then deliver final SoC DV signoff using regressions, coverage, and DV-to-spec traceability aligned to ISO26262.

Location: Bengaluru

Workplace: Onsite

Employment Type: Full time

Job Function: Design (Product/UX/UI/Visual)

Seniority: Mid level

Key Responsibilities

•Own IP/subsystem/SoC DV from spec definition through post-silicon verification and resolve customer issues as needed.
•Partner with the architecture team during spec definition and define the verification strategy and verification plan to achieve 100% spec regression traceability and signoff metrics.
•Perform subsystem/SoC verification covering functional and firmware scenarios in RTL/PARTL and GLS/PAGLS modes.
•Own the DV environment including TB development/enhancements, checker and coverage monitor definitions, and DV flow updates.
•Complete final SoC DV signoff using regressions, coverage metrics, and DV-to-spec traceability using C and/or SV-UVM while adhering to ISO26262 guidelines.

Key Requirements

•2-5 years of DV experience in SS/SOC/post-silicon DV with a Bachelor’s or Master’s degree in EE/ECE/CS or related specializations.
•Experience with C-based SoC DV and DV flow ownership for functional/formal verification.
•Deep understanding of UVM/SystemVerilog and verification of AMS/GLS/PAGLS/CPF/UPF scenarios.
•Strong digital design fundamentals and computer architecture/bus protocols; debugging skills with Verilog/VHDL designs.
•Experience with Cadence tools (Xcelium, vManager, Formal apps, safety simulator) or similar DV tools/flows.

Experience:2-5 yearsSemiconductorSoCPost-silicon verification

Education:Bachelor's

Skills:DebuggingProblem-solvingCommunicationCollaborationFocus

Languages:US

Tech Stack:CPythonPerlShellSystem VerilogUVMVerilogVHDLRTLPARTLGLSPAGLSTB developmentCheckersCoverage monitorDV flowCadence XceliumCadence vManagerCadence FormalSafety simulator

Company Brief

Texas Instruments

Designs and manufactures semiconductors and analog chips used in industrial, automotive, personal electronics, communications, and enterprise systems. It is one of the world’s largest semiconductor companies, with a broad portfolio of embedded processing and power products.

Industry: Electronics Manufacturing

Company Size: Enterprise (1,001+ employees)

Revenue: USD 1B+

Growth: Public Company

Valuation: Public Company (Market Cap in USD)

Funding: IPO / Publicly Listed

Headquarters: Dallas, United States

Founded: 1930

Website LinkedIn

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Texas Instruments

Recent

Design Verification Engineer

✓ Verified Job

Canonical indexed version, validated from employer's careers page.

Source: Company careers pageValidated by: Fursa AI

Last checked: 13 hours agoStatus: Live

Job Summary

Location: Bengaluru

Workplace: Onsite

Employment Type: Full time

Job Function: Design (Product/UX/UI/Visual)

Seniority: Mid level

Key Responsibilities

•Own IP/subsystem/SoC DV from spec definition through post-silicon verification and resolve customer issues as needed.
•Partner with the architecture team during spec definition and define the verification strategy and verification plan to achieve 100% spec regression traceability and signoff metrics.
•Perform subsystem/SoC verification covering functional and firmware scenarios in RTL/PARTL and GLS/PAGLS modes.
•Own the DV environment including TB development/enhancements, checker and coverage monitor definitions, and DV flow updates.
•Complete final SoC DV signoff using regressions, coverage metrics, and DV-to-spec traceability using C and/or SV-UVM while adhering to ISO26262 guidelines.

Key Requirements

•2-5 years of DV experience in SS/SOC/post-silicon DV with a Bachelor’s or Master’s degree in EE/ECE/CS or related specializations.
•Experience with C-based SoC DV and DV flow ownership for functional/formal verification.
•Deep understanding of UVM/SystemVerilog and verification of AMS/GLS/PAGLS/CPF/UPF scenarios.
•Strong digital design fundamentals and computer architecture/bus protocols; debugging skills with Verilog/VHDL designs.
•Experience with Cadence tools (Xcelium, vManager, Formal apps, safety simulator) or similar DV tools/flows.

Experience:2-5 yearsSemiconductorSoCPost-silicon verification

Education:Bachelor's

Skills:DebuggingProblem-solvingCommunicationCollaborationFocus

Languages:US

Tech Stack:CPythonPerlShellSystem VerilogUVMVerilogVHDLRTLPARTLGLSPAGLSTB developmentCheckersCoverage monitorDV flowCadence XceliumCadence vManagerCadence FormalSafety simulator

Company Brief

Texas Instruments

Industry: Electronics Manufacturing

Company Size: Enterprise (1,001+ employees)

Revenue: USD 1B+

Growth: Public Company

Valuation: Public Company (Market Cap in USD)

Funding: IPO / Publicly Listed

Headquarters: Dallas, United States

Founded: 1930

Website LinkedIn