Lead Design Engineer

Cadence Design Systems
Bengaluru
Workplace: OnsiteFull timeFunction: Design (Product/UX/UI/Visual)Experience: 3+ yearsEducation: bachelorsSkills: ["Analytical thinking","Communication","Collaboration","Engineering judgment","Ownership"]

Develop high-speed, low-power SerDes transceivers by translating link-level system requirements into silicon-ready analog mixed-signal circuit architectures. Design and verify key SerDes blocks (TX, RX, equalization, ADC/DAC, PLL/DLL, clocking, regulators, biasing, and calibration), optimize performance across PVT and parasitics, and create behavioral models for mixed-signal verification. Partner with layout and signal-integrity teams for signoff, then support tapeout through bring-up, characterization, debug, and production release.

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Cadence Design Systems
Cadence Design Systems
4 days ago

Lead Design Engineer

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Last checked: 1 hour agoStatus: Live

Job Summary

Develop high-speed, low-power SerDes transceivers by translating link-level system requirements into silicon-ready analog mixed-signal circuit architectures. Design and verify key SerDes blocks (TX, RX, equalization, ADC/DAC, PLL/DLL, clocking, regulators, biasing, and calibration), optimize performance across PVT and parasitics, and create behavioral models for mixed-signal verification. Partner with layout and signal-integrity teams for signoff, then support tapeout through bring-up, characterization, debug, and production release.
Location: Bengaluru
Workplace: Onsite
Employment Type: Full time
Job Function: Design (Product/UX/UI/Visual)
Seniority: Mid level

Key Responsibilities

  • •Design and verify high-speed SerDes blocks including TX drivers, serializers, RX front ends, CTLEs, samplers, comparators, ADCs, DACs, PLLs, DLLs, clocking, regulators, bias circuits, and calibration loops.
  • •Translate link-level requirements into circuit specifications and optimize performance across PVT, mismatch, aging, and extracted parasitics.
  • •Develop behavioral models and support mixed-signal and top-level verification activities.
  • •Collaborate with layout and signal-integrity teams for physical implementation, channel/package effects, and post-layout signoff.
  • •Support tapeout through silicon bring-up, characterization, debug, and production release, including documentation and technical design reviews.

Key Requirements

  • •B.S. in Electrical Engineering (or related) with 3+ years of relevant experience, or an M.S. with 1+ years.
  • •Strong analog CMOS fundamentals across noise, jitter, feedback, signal integrity, and data converters.
  • •Hands-on transistor-level design experience with high-speed SerDes circuits.
  • •Excellent proficiency with Cadence Virtuoso, Spectre, Spectre RF, ADE, parasitic extraction, and mixed-signal verification flows.
  • •Strong analytical thinking and engineering judgment with clear communication and collaboration.
Experience:3+ yearsSerDesAnalog CMOSMixed-signalData centerNetworkingAIHigh-performance computing
Education:Bachelor's in Electrical Engineering
Skills:Analytical thinkingCommunicationCollaborationEngineering judgmentOwnership
Tech Stack:Cadence VirtuosoSpectreSpectre RFADEParasitic extractionPAM4NRZEthernetPCIeCXLMATLABCSystemVerilogVerilog-AVerilogPerlPython

Company Brief

Cadence Design Systems
Provides electronic design automation (EDA) software, IP, and services for semiconductor and systems companies to design, verify, and implement integrated circuits, systems-on-chip, and electronic systems across industries including communications, automotive, and consumer electronics.
Industry: Developer Tools
Company Size: Enterprise (1,001+ employees)
Revenue: USD 1B+
Growth: Public Company
Valuation: Public Company (Market Cap in USD)
Funding: IPO / Publicly Listed
Headquarters: San Jose, United States
Founded: 1988
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