Physical Design Engineer II (PNR/Physical Verification/STA/EMIR)

Cadence Design Systems
Canada
Workplace: OnsiteFull timeFunction: Design (Product/UX/UI/Visual)Experience: 3+ yearsEducation: bachelorsSkills: ["Static timing analysis","DRC","LVS","Antenna","ERC","DFM","Clock tree synthesis","Place and route","Floor planning","Timing closure","EM/IR signoff","Physical verification"]

Join Cadence as a Physical Design Engineer II focusing on PNR, physical verification, STA/EMIR, and flow development. Lead next-generation physical design in advanced nodes, collaborate with RTL and Analog teams to ensure successful tapeouts, and perform floor planning, timing closure, signoffs, and DFM/DRC/LVS reviews.

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Cadence Design Systems
Cadence Design Systems
2 months ago

Physical Design Engineer II (PNR/Physical Verification/STA/EMIR)

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Last checked: 7 hours agoStatus: Live

Job Summary

Join Cadence as a Physical Design Engineer II focusing on PNR, physical verification, STA/EMIR, and flow development. Lead next-generation physical design in advanced nodes, collaborate with RTL and Analog teams to ensure successful tapeouts, and perform floor planning, timing closure, signoffs, and DFM/DRC/LVS reviews.
Location: Canada
Workplace: Onsite
Employment Type: Full time
Job Function: Design (Product/UX/UI/Visual)

Key Responsibilities

  • •Lead or participate in next-generation physical design, methodology, and flow development in advanced technology nodes
  • •Perform physical design implementation including floor planning, power grid design, place-and-route, clock tree synthesis, timing closure, and power/signals integrity signoff
  • •Execute physical verification activities (DRC/LVS/Antenna), EM/IR signoff, and DFM closure
  • •Fix physical design violations (DRC, DFM, LVS, ANT, ERC) and conduct static timing analysis
  • •Collaborate with RTL and Analog teams to ensure successful tapeouts

Key Requirements

  • •Bachelor or above degree in EE/CS/IT with 3+ years of experience
  • •Extensive knowledge of design rules for processes of N7/N5 and below
  • •Knowledge of scripting languages and usage in methodology
  • •Ability to fix physical design violations (DRC, DFM, LVS, ANT, ERC)
  • •Deep experience in static timing analysis
Experience:3+ yearsSemiconductorsVLSIASIC
Education:Bachelor's
Skills:Static timing analysisDRCLVSAntennaERCDFMClock tree synthesisPlace and routeFloor planningTiming closureEM/IR signoffPhysical verification
Languages:English
Tech Stack:TCLPythonEDA toolsScripting

Company Brief

Cadence Design Systems
Provides electronic design automation (EDA) software, IP, and services for semiconductor and systems companies to design, verify, and implement integrated circuits, systems-on-chip, and electronic systems across industries including communications, automotive, and consumer electronics.
Industry: Developer Tools
Company Size: Enterprise (1,001+ employees)
Revenue: USD 1B+
Growth: Public Company
Valuation: Public Company (Market Cap in USD)
Funding: IPO / Publicly Listed
Headquarters: San Jose, United States
Founded: 1988
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