Design Verification Engineer-System Verilog/UVM
AMD
San Jose
Workplace: HybridFull timeFunction: Design (Product/UX/UI/Visual)Education: bachelorsSkills: ["Verilog","SystemVerilog","UVM","C","C++","Assembly","Python","Gate level simulation","Power verification","Reset verification"]Design verification engineer on front-end verification for AMD/Xilinx programmable devices, collaborating across multi-site teams to define verification strategies, build test benches with SystemVerilog/UVM, and ensure silicon readiness through debug and coverage analysis.
