NVIDIA

3 months ago

Senior Mask Design Engineer

✓ Verified Job

Canonical indexed version, validated from employer's careers page.

Source: Company careers pageValidated by: Fursa AI

Last checked: 13 hours agoStatus: Live

Job Summary

Senior Mask Layout Design Engineer responsible for collaborative, multi-disciplinary layout work for mixed-signal circuits in sub-micron CMOS technologies. You’ll perform floor planning, custom layout, DRC/LVS verification, and collaboration with ASIC and mixed-signal teams to enable integration into VLSI products, with exposure to Cadence tools and foundry interactions.

Location: Santa Clara

Workplace: Hybrid

Employment Type: Full time

Job Function: Design (Product/UX/UI/Visual)

Seniority: Manager level

Key Responsibilities

•Collaborate with a multi-disciplinary team of Photonics, CMOS, Electronics, and Systems engineers to deliver layout solutions.
•Perform physical layout for mixed-signal functions (PLL, high-speed I/O, general I/O, ESD structures) in sub-micron CMOS technologies using Cadence tools.
•Work with ASIC and mixed-signal engineers to customize designs for integration in VLSI products.
•Handle floor planning, custom layout, and verification against design rules and schematics.
•Engage in fill, post-processing, DRC mitigation, and interactions with foundries.

Pay and Benefits

Salary: USD 132,000 - 207,000 annually

Equity and Bonus:Equity

Perks:Equity

Key Requirements

•BS in Electrical Engineering (or equivalent experience)
•At least 6+ years of hands-on layout design experience
•Deep understanding of analog circuit layout concepts in submicron CMOS technologies; experience with Cadence custom circuit design tools - particularly virtuoso
•Experience running and debugging DRC and LVS with verification tools such as Dracula, Hercules, Calibre, Primeyield
•Proficiency in scripting languages like Perl, Python, SKILL; knowledge of DRC and LVS checking flows; ability to customize DRC and LVS

Experience:6+ yearsSemiconductorsElectronics

Education:Bachelor's

Skills:TeamworkInterpersonalCollaboration

Tech Stack:CadenceVirtuosoDRCLVSDraculaHerculesCalibrePrimeyieldPerlPythonSKILL

Company Brief

NVIDIA

Designs and manufactures GPUs, AI accelerators, and system-on-chip products for gaming, data centers, professional visualization, and automotive markets, enabling advanced graphics, AI, and high-performance computing solutions worldwide.

Industry: Electronics Manufacturing

Company Size: Enterprise (1,001+ employees)

Revenue: USD 1B+

Growth: Public Company

Valuation: Public Company (Market Cap in USD)

Funding: IPO / Publicly Listed

Headquarters: Santa Clara, United States

Founded: 1993

Glassdoor: 4.3

Website LinkedIn Glassdoor

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NVIDIA

3 months ago

Senior Mask Design Engineer

✓ Verified Job

Canonical indexed version, validated from employer's careers page.

Source: Company careers pageValidated by: Fursa AI

Last checked: 13 hours agoStatus: Live

Job Summary

Location: Santa Clara

Workplace: Hybrid

Employment Type: Full time

Job Function: Design (Product/UX/UI/Visual)

Seniority: Manager level

Key Responsibilities

•Collaborate with a multi-disciplinary team of Photonics, CMOS, Electronics, and Systems engineers to deliver layout solutions.
•Perform physical layout for mixed-signal functions (PLL, high-speed I/O, general I/O, ESD structures) in sub-micron CMOS technologies using Cadence tools.
•Work with ASIC and mixed-signal engineers to customize designs for integration in VLSI products.
•Handle floor planning, custom layout, and verification against design rules and schematics.
•Engage in fill, post-processing, DRC mitigation, and interactions with foundries.

Pay and Benefits

Salary: USD 132,000 - 207,000 annually

Equity and Bonus:Equity

Perks:Equity

Key Requirements

•BS in Electrical Engineering (or equivalent experience)
•At least 6+ years of hands-on layout design experience
•Deep understanding of analog circuit layout concepts in submicron CMOS technologies; experience with Cadence custom circuit design tools - particularly virtuoso
•Experience running and debugging DRC and LVS with verification tools such as Dracula, Hercules, Calibre, Primeyield
•Proficiency in scripting languages like Perl, Python, SKILL; knowledge of DRC and LVS checking flows; ability to customize DRC and LVS

Experience:6+ yearsSemiconductorsElectronics

Education:Bachelor's

Skills:TeamworkInterpersonalCollaboration

Tech Stack:CadenceVirtuosoDRCLVSDraculaHerculesCalibrePrimeyieldPerlPythonSKILL

Company Brief

NVIDIA

Industry: Electronics Manufacturing

Company Size: Enterprise (1,001+ employees)

Revenue: USD 1B+

Growth: Public Company

Valuation: Public Company (Market Cap in USD)

Funding: IPO / Publicly Listed

Headquarters: Santa Clara, United States

Founded: 1993

Glassdoor: 4.3

Website LinkedIn Glassdoor