Principal Analog Mixed Signal Circuit Design Engineer, SERDES

Plan, build, and execute verification for new and existing features of SERDES IP to ensure bug-free final designs. Design wireline transceiver building blocks such as PLL, clock distribution, receiver/transmitter front-ends, serializer, and deserializer. Lead and present at design review meetings with worldwide teams, conduct peer reviews of circuit design and verification results, and collaborate with validation to evaluate silicon results.