Formal Verification Architect

AMD
Austin
Workplace: HybridFull timeFunction: Software EngineeringEducation: mastersSkills: ["Leadership","Mentoring","Analytical problem-solving","Collaboration","Continuous improvement"]

Drive formal verification for complex IP and SoC designs within AMD’s NBIO IOHUB team. Lead and mentor engineers, define verification architecture and methodologies, and build reusable formal verification environments, properties, and infrastructure. Own verification test planning and closure, including connectivity, deadlock/livelock, and protocol verification. Triage tool failures and collaborate with design, validation, and post-silicon teams to achieve verification sign-off and high-quality silicon.

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FursaFursa
AMD
AMD
23 hours ago

Formal Verification Architect

✓ Verified Job

Canonical indexed version, validated from employer's careers page.

Source: Company careers pageValidated by: Fursa AI
Last checked: 8 hours agoStatus: Live
Reposted: similar role first listed 1 week ago

Job Summary

Drive formal verification for complex IP and SoC designs within AMD’s NBIO IOHUB team. Lead and mentor engineers, define verification architecture and methodologies, and build reusable formal verification environments, properties, and infrastructure. Own verification test planning and closure, including connectivity, deadlock/livelock, and protocol verification. Triage tool failures and collaborate with design, validation, and post-silicon teams to achieve verification sign-off and high-quality silicon.
Location: Austin
Workplace: Hybrid
Employment Type: Full time
Job Function: Software Engineering
Seniority: Manager level

Key Responsibilities

  • •Lead and mentor a team of formal verification engineers across multiple IP and SoC projects.
  • •Define and drive formal verification architecture, methodologies, and development plans with IP architects and design teams.
  • •Develop formal verification test plans and execute verification closure strategies.
  • •Architect and maintain reusable formal verification environments, properties, components, and infrastructure.
  • •Perform and debug connectivity, deadlock/livelock, and protocol verification; triage failures and collaborate to resolve issues through sign-off.

Key Requirements

  • •Deep expertise in formal verification methodologies for complex digital designs and SoCs.
  • •Proven leadership experience guiding technical teams and mentoring engineers.
  • •Strong verification skills including formal verification (static/dynamic), assertion-based verification, FPV/DPV, and formal test planning.
  • •Experience with CDC and RDC formal verification methodologies, with JasperGold CDC/RDC and Connectivity apps strongly preferred.
  • •Strong understanding of digital design and computer architecture, including CPU/GPU, interconnect/bus/NOC, memory controllers, and cache, plus SystemVerilog/Verilog/VHDL familiarity and scripting skills as an asset.
Education:Master's in Electrical, Electronics, Computer or Computer Science
Skills:LeadershipMentoringAnalytical problem-solvingCollaborationContinuous improvement
Languages:En-us
Tech Stack:Formal verificationAssertion-based verificationFPVDPVCDCRDCJasperGoldConnectivity appsSECLECAssume-guaranteeAbstractionDecompositionJasperVC-formalUVMSystemVerilogVerilogVHDLScripting

Eligibility

Work Authorization:Authorization required. Sponsorship not provided.

Company Brief

AMD
Designs and produces semiconductor products including CPUs, GPUs, and adaptive SoCs for consumer, enterprise, and embedded markets, competing across PCs, data centers, and gaming industries.
Industry: Electronics Manufacturing
Company Size: Enterprise (1,001+ employees)
Revenue: USD 1B+
Growth: Public Company
Valuation: Public Company (Market Cap in USD)
Funding: IPO / Publicly Listed
Headquarters: Santa Clara, United States
Founded: 1969
Glassdoor
Glassdoor: 3.9
WebsiteLinkedIn