Physical Design and Timing Engineer Intern - Summer 2027

NVIDIA
Santa Clara
Workplace: OnsiteInternshipUSD 20 - 71 hourlyFunction: Design (Product/UX/UI/Visual)Education: mastersSkills: ["Creativity","Collaboration","Problem-solving"]

Drive physical design, power, and timing closure for high-frequency, low-power chip designs. Work across RTL to GDSII, run physical design experiments, and help build flows and methodologies. Contribute to areas like static timing analysis, power analysis and reduction, logic synthesis, equivalence checking, and physical optimization (placement, routing, clock tree). Use industry EDA tools and programming/scripting to accelerate design automation, analysis, and optimization.

Loading

Loading job details...

Preparing the role view and application actions.

FursaFursa
NVIDIA
NVIDIA
1 day ago

Physical Design and Timing Engineer Intern - Summer 2027

✓ Verified Job

Canonical indexed version, validated from employer's careers page.

Source: Company careers pageValidated by: Fursa AI
Last checked: 2 hours agoStatus: Live

Job Summary

Drive physical design, power, and timing closure for high-frequency, low-power chip designs. Work across RTL to GDSII, run physical design experiments, and help build flows and methodologies. Contribute to areas like static timing analysis, power analysis and reduction, logic synthesis, equivalence checking, and physical optimization (placement, routing, clock tree). Use industry EDA tools and programming/scripting to accelerate design automation, analysis, and optimization.
Location: Santa Clara
Workplace: Onsite
Employment Type: Internship
Job Function: Design (Product/UX/UI/Visual)
Seniority: Entry level

Key Responsibilities

  • •Drive physical design, power, and timing closure for high-frequency and low-power designs.
  • •Support frontend and backend implementation in select areas from RTL to GDSII.
  • •Run physical design experiments and help develop flows and methodologies.
  • •Apply static timing and power analysis techniques to enable power reduction efforts.
  • •Use physical optimization techniques (e.g., placement, routing, clock tree) and EDA tools to improve design outcomes.

Pay and Benefits

Salary: USD 20 - 71 hourly

Key Requirements

  • •Pursuing an MS or Ph.D. in Electrical or Computer Engineering.
  • •Familiarity with applying AI/ML techniques to physical design workflows to accelerate design, analysis, or automation.
  • •Knowledge or experience with Static Timing Analysis (STA), power analysis, and power reduction.
  • •Some experience in logic synthesis and equivalence checking.
  • •Experience with physical optimization such as placement, routing, and clock tree.
Education:Master's in Electrical or Computer Engineering
Skills:CreativityCollaborationProblem-solving
Tech Stack:AI/MLLLMStatic Timing Analysis (STA)Power analysisLogic synthesisEquivalence checkingPlacementRoutingClock treeRTLGDSIICadenceSynopsysSiemensPerlTclMakePython

Company Brief

NVIDIA
Designs and manufactures GPUs, AI accelerators, and system-on-chip products for gaming, data centers, professional visualization, and automotive markets, enabling advanced graphics, AI, and high-performance computing solutions worldwide.
Industry: Electronics Manufacturing
Company Size: Enterprise (1,001+ employees)
Revenue: USD 1B+
Growth: Public Company
Valuation: Public Company (Market Cap in USD)
Funding: IPO / Publicly Listed
Headquarters: Santa Clara, United States
Founded: 1993
Glassdoor
Glassdoor: 4.3
WebsiteLinkedInGlassdoor