STA (Static Timing Analysis) Design Intern

Evaluate timing margins for semiconductor ASIC/SoC logic designs to help ensure chips meet target speeds without errors. Run static timing analysis (STA), analyze slack, and help fix setup/hold violations. Support constraint management by creating, updating, and debugging timing exceptions. Write scripts to improve and speed up existing EDA flows, working alongside senior engineers. Onsite schedule requires 4 days per week and a 6-month internship commitment.