Design Verification Engineer (Silicon Engineering)

SpaceX
Austin
Workplace: OnsiteFull timeFunction: Design (Product/UX/UI/Visual)Experience: 1+ yearsEducation: bachelorsSkills: ["Problem-solving","Communication","Hands-on","Self-starter","Adaptability"]

Develop digital ASIC verification at block and system level for space and ground Starlink infrastructure. Write and review test plans, build test harnesses and sequences, and create SystemVerilog testbench infrastructure (UVM and non-UVM). Execute regressions, drive code and functional coverage closure, automate test-case generation with Python and MATLAB, and contribute across pre-silicon verification, chip bring-up, and post-silicon validation.

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FursaFursa
SpaceX
SpaceX
2 months ago

Design Verification Engineer (Silicon Engineering)

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Source: Company careers pageValidated by: Fursa AI
Last checked: 2 hours agoStatus: Live

Job Summary

Develop digital ASIC verification at block and system level for space and ground Starlink infrastructure. Write and review test plans, build test harnesses and sequences, and create SystemVerilog testbench infrastructure (UVM and non-UVM). Execute regressions, drive code and functional coverage closure, automate test-case generation with Python and MATLAB, and contribute across pre-silicon verification, chip bring-up, and post-silicon validation.
Location: Austin
Workplace: Onsite
Employment Type: Full time
Job Function: Design (Product/UX/UI/Visual)
Seniority: Entry level

Key Responsibilities

  • •Verify digital ASICs at block and system level.
  • •Write and review test plans; develop test harnesses and test sequences.
  • •Develop SystemVerilog testbench infrastructure (UVM and non-UVM), including DSP blocks.
  • •Run test regressions and drive code and functional coverage closure.
  • •Automate test-case generation using Python and MATLAB, supporting pre-silicon verification, chip bring-up, and post-silicon validation.

Key Requirements

  • •Bachelor’s degree in electrical engineering, computer science, or computer engineering.
  • •1+ years of experience with design verification and test bench development.
  • •Experience developing SystemVerilog testbench infrastructure (UVM and/or non-UVM).
  • •Strong object-oriented programming knowledge and coding skills.
  • •Experience with verification methodologies such as UVM and/or constrained random verification, including test plans and coverage models.
Experience:1+ years
Education:Bachelor's
Skills:Problem-solvingCommunicationHands-onSelf-starterAdaptability
Languages:English
Tech Stack:ASICSystemVerilogUVMPythonMATLABRTLTestbenchDSP

Eligibility

Nationality:US National

Company Brief

SpaceX
Designs, manufactures, and launches advanced rockets and spacecraft for commercial and government customers, aiming to reduce space transportation costs and enable human life on Mars through reusable launch vehicles and integrated space systems.
Industry: Aerospace Manufacturing
Company Size: Enterprise (1,001+ employees)
Growth: Established Company
Valuation: Hectocorn (USD 100B+)
Funding: Series E+
Headquarters: Hawthorne, United States
Founded: 2002
Glassdoor
Glassdoor: 4.2
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