Design Verification Engineer (Silicon Engineering)

Develop digital ASIC verification at block and system level for space and ground Starlink infrastructure. Write and review test plans, build test harnesses and sequences, and create SystemVerilog testbench infrastructure (UVM and non-UVM). Execute regressions, drive code and functional coverage closure, automate test-case generation with Python and MATLAB, and contribute across pre-silicon verification, chip bring-up, and post-silicon validation.