Leader, ASIC Engineering | RTL, Datapath, Network Processing Unit

Cisco
Bengaluru
Workplace: OnsiteFull timeFunction: Hardware, Embedded & Systems EngineeringExperience: 13+ yearsEducation: bachelorsSkills: ["Leadership","Interpersonal skills","Communication","Mentoring","Collaboration"]

Lead ASIC engineering for Cisco’s SiliconOne team, driving RTL/SoC development from specification through tape-out and lab validation. Manage teams defining, designing, and verifying ASICs and subsystems to meet stringent PPA goals for high-performance, power-efficient, high-volume products. Own implementation across timing analysis, power optimization, verification, and flow automation, while partnering cross-functionally to deliver quality silicon aligned to Cisco platforms.

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FursaFursa
Cisco
Cisco
14 hours ago

Leader, ASIC Engineering | RTL, Datapath, Network Processing Unit

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Last checked: 14 hours agoStatus: Live

Job Summary

Lead ASIC engineering for Cisco’s SiliconOne team, driving RTL/SoC development from specification through tape-out and lab validation. Manage teams defining, designing, and verifying ASICs and subsystems to meet stringent PPA goals for high-performance, power-efficient, high-volume products. Own implementation across timing analysis, power optimization, verification, and flow automation, while partnering cross-functionally to deliver quality silicon aligned to Cisco platforms.
Location: Bengaluru
Workplace: Onsite
Employment Type: Full time
Job Function: Hardware, Embedded & Systems Engineering
Seniority: Manager level

Key Responsibilities

  • •Lead ASIC engineering teams delivering high-performance, power-efficient, reliable ASICs aligned to Cisco product platforms.
  • •Define, design, and verify ASICs and ASIC subsystems to meet power, performance, and area (PPA) goals.
  • •Drive implementation across specification, design, timing analysis, power optimization, verification, and flow automation.
  • •Oversee documentation, development, and validation of ASIC subsystems to ensure robust designs and high-volume readiness.
  • •Lead technical direction and collaboration across Architecture, DV, PD, Emulation, SW, PSV, and Silicon Operations; run design meetings, code reviews, and postmortems.

Key Requirements

  • •BS/MS with 15+ years (BS) or 13+ years (MS) of hands-on experience in large-scale, high-performance ASIC development.
  • •Led an ASIC design team for at least 4 years, including architecture and implementation specification creation.
  • •Expertise in RTL development using Verilog and SystemVerilog, plus VCS, Spyglass, CDC, and formal verification.
  • •Gate-level understanding of RTL and synthesis, with experience in system debug and SW/HW bring-up.
  • •Strong written/verbal communication and leadership skills.
Experience:13+ years
Education:Bachelor's
Skills:LeadershipInterpersonal skillsCommunicationMentoringCollaboration
Tech Stack:ASICSoCRTLVerilogSystemVerilogVCSSpyglassCDCFormal verificationGate-levelSynthesisTiming analysisPower optimizationFlow automationTape-outLab validationSystem validationEmulation

Company Brief

Cisco
Global technology company that designs, manufactures, and sells networking hardware, telecommunications equipment, and high-technology services and products for enterprises, service providers, and governments worldwide.
Industry: Networking Equipment
Company Size: Enterprise (1,001+ employees)
Revenue: USD 1B+
Growth: Public Company
Valuation: Public Company (Market Cap in USD)
Funding: IPO / Publicly Listed
Headquarters: San Jose, United States
Founded: 1984
Glassdoor
Glassdoor: 4.0
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