Lead Software Engineer - Logic Synthesis

Cadence Design Systems
Shanghai
Workplace: OnsiteFull timeFunction: Software EngineeringExperience: 3-5 yearsEducation: bachelorsSkills: ["Communication","Attention to details","Ability to work in multi-site/multi-person projects"]

Develop and maintain Cadence’s logic synthesizer for Palladium, delivering new VHDL/Verilog feature support. Own logic optimization and performance improvements, collaborating across multi-site teams to deliver RTL modeling and verification-ready designs. Apply expertise in C/C++ and operating system concepts, with preferred experience in RTL modeling (BFMs), UVM verification, and EDA/CAD tool development. AI coding tool familiarity (Copilot/Claude Code) is a plus.

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Cadence Design Systems
Cadence Design Systems
1 day ago

Lead Software Engineer - Logic Synthesis

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Source: Company careers pageValidated by: Fursa AI
Last checked: 4 hours agoStatus: Live
Reposted: similar role first listed 2 months ago

Job Summary

Develop and maintain Cadence’s logic synthesizer for Palladium, delivering new VHDL/Verilog feature support. Own logic optimization and performance improvements, collaborating across multi-site teams to deliver RTL modeling and verification-ready designs. Apply expertise in C/C++ and operating system concepts, with preferred experience in RTL modeling (BFMs), UVM verification, and EDA/CAD tool development. AI coding tool familiarity (Copilot/Claude Code) is a plus.
Location: Shanghai
Workplace: Onsite
Employment Type: Full time
Job Function: Software Engineering
Seniority: Mid level

Key Responsibilities

  • •Develop and maintain the synthesizer for Palladium.
  • •Implement new VHDL/Verilog feature support in the synthesizer.
  • •Perform logic optimization to improve synthesizer performance.
  • •Improve synthesizer performance through targeted development.
  • •Collaborate with multi-site teams on synthesizer development projects.

Key Requirements

  • •Bachelor’s or Master’s degree in EE/CS/CE with 3–5 years of industry experience.
  • •Proficiency with C/C++ and operating system concepts.
  • •Experience with design modeling using Verilog/SystemVerilog, VHDL, or SysC.
  • •Knowledge of RTL modeling of BFMs and exposure to verification methodologies using UVM and SC/TLM.
  • •EDA/CAD tool development or logic design verification experience; AI tool experience (Copilot/Claude Code) is preferred.
Experience:3-5 years
Education:Bachelor's in EE/CS/CE
Skills:CommunicationAttention to detailsAbility to work in multi-site/multi-person projects
Tech Stack:C/C++Operating system conceptsVerilogSystemVerilogVHDLSysCRTL modelingBFMsUVMSC/TLMEDA/CAD toolsCopilotClaude codeLogic synthesisSynthesizerPalladium

Company Brief

Cadence Design Systems
Provides electronic design automation (EDA) software, IP, and services for semiconductor and systems companies to design, verify, and implement integrated circuits, systems-on-chip, and electronic systems across industries including communications, automotive, and consumer electronics.
Industry: Developer Tools
Company Size: Enterprise (1,001+ employees)
Revenue: USD 1B+
Growth: Public Company
Valuation: Public Company (Market Cap in USD)
Funding: IPO / Publicly Listed
Headquarters: San Jose, United States
Founded: 1988
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