Design-for-Test (DFT) Engineer — ASIC Backend – (Associate, Experienced, or Lead)

Boeing
United States
Workplace: OnsiteFull timeUSD 98,600 - 197,800 annuallyFunction: Design (Product/UX/UI/Visual)Experience: 2-9 yearsEducation: bachelorsSkills: ["Analytical","Problem-solving","Communication","Collaboration"]

Drive architecture, verification, and post-silicon validation for leading-edge ASICs as part of Boeing’s Electronic Products DFT team. Design and integrate DFT test access mechanisms (TAP/JTAG, IJTAG/IEEE 1687, Boundary Scan/IEEE 1149.1), memory BIST, scan compression, and ATPG pattern generation. Perform coverage optimization, silicon debug/bring-up, and collaborate across the chip design flow and external interfaces in an aerospace environment.

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FursaFursa
Boeing
Boeing
4 days ago

Design-for-Test (DFT) Engineer — ASIC Backend – (Associate, Experienced, or Lead)

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Source: Company careers pageValidated by: Fursa AI
Last checked: 19 hours agoStatus: Live

Job Summary

Drive architecture, verification, and post-silicon validation for leading-edge ASICs as part of Boeing’s Electronic Products DFT team. Design and integrate DFT test access mechanisms (TAP/JTAG, IJTAG/IEEE 1687, Boundary Scan/IEEE 1149.1), memory BIST, scan compression, and ATPG pattern generation. Perform coverage optimization, silicon debug/bring-up, and collaborate across the chip design flow and external interfaces in an aerospace environment.
Location: United States
Workplace: Onsite
Employment Type: Full time
Job Function: Design (Product/UX/UI/Visual)
Seniority: Mid level

Key Responsibilities

  • •Design and implement DFT architectures including TAP/JTAG, IJTAG (IEEE 1687), Boundary Scan (BSCAN), MBIST, and scan compression.
  • •Develop and validate TAP/JTAG and IJTAG infrastructure, BSDL/ICL/PDL artifacts, and ATPG pattern generation.
  • •Drive pattern generation, coverage optimization, memory test validation, and silicon debug (scan, at-speed, bring-up).
  • •Integrate DFT features across the chip design flow and collaborate with cross-functional teams for robust DFT integration.
  • •Coordinate with external partners/customers on custom DFT interfaces and security requirements when applicable.
Travel: Low travel

Pay and Benefits

Salary: USD 98,600 - 197,800 annually
Perks:Health InsuranceFlexible SpendingRetirement SavingsLife InsuranceDisability Insurance

Key Requirements

  • •Ability to obtain a U.S. Secret security clearance, with the U.S. Government requiring U.S. citizenship as a condition of employment.
  • •Bachelor of Science degree in Engineering (Electrical, Mechanical, or Aeronautical) or Computer Science, Data Science, Mathematics, Physics, Chemistry, or non-U.S. equivalent directly related to the work.
  • •2+ years of experience in Design for Testability (DFT) or equivalent.
  • •Strong knowledge of ASIC/logic design flow, HDL (Verilog/SystemVerilog), static timing analysis, and ECO processes.
  • •Hands-on experience with TAP/JTAG, IJTAG (IEEE 1687), Boundary Scan (IEEE 1149.1), MBIST, scan compression, ATPG, at-speed test, and silicon debug.
Experience:2-9 yearsAerospaceSemiconductorsASIC
Education:Bachelor's
Skills:AnalyticalProblem-solvingCommunicationCollaboration
Tech Stack:TAP/JTAGIJTAGIEEE 1687Boundary ScanIEEE 1149.1MBISTScan compressionBSDLICLPDLATPGAt-speed testECOStatic timing analysisVerilogSystemVerilogHDLTclPerlPython

Eligibility

Nationality:US National
Work Authorization:Authorization required. Sponsorship not provided.
Security Clearance:Secret

Company Brief

Boeing
Designs, manufactures, and services commercial airplanes, defense systems, space vehicles, and related products and services globally. Boeing serves airlines, governments, and commercial customers with aerospace and defense technologies and integrated support solutions.
Industry: Aerospace Manufacturing
Company Size: Enterprise (1,001+ employees)
Revenue: USD 1B+
Growth: Public Company
Valuation: Public Company (Market Cap in USD)
Funding: IPO / Publicly Listed
Headquarters: Arlington, United States
Founded: 1916
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Glassdoor: 3.7
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