Distinguished Technologist - Memory/Storage Utilization & Data Placement Architect

HP
Texas, Palo Alto
Workplace: OnsiteFull timeUSD 190,000 - 274,000 annuallyFunction: Hardware, Embedded & Systems EngineeringExperience: 12+ yearsEducation: bachelorsSkills: ["Effective communication","Results orientation","Learning agility","Digital fluency","Customer centricity"]

Define how memory and storage work together as a unified data hierarchy for AI workloads. Optimize data placement, movement, and persistence across memory tiers, improving paging, prefetching, and streaming for training and inference. Partner with software, OS/runtime, and hardware teams to co-optimize models and enable storage-as-memory approaches. Lead long-term technology roadmaps, communicate strategy to executives, and mentor engineers while driving R&D.

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FursaFursa
HP
HP
3 months ago

Distinguished Technologist - Memory/Storage Utilization & Data Placement Architect

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Last checked: 6 hours agoStatus: Live
Reposted: similar role first listed 1 month ago

Job Summary

Define how memory and storage work together as a unified data hierarchy for AI workloads. Optimize data placement, movement, and persistence across memory tiers, improving paging, prefetching, and streaming for training and inference. Partner with software, OS/runtime, and hardware teams to co-optimize models and enable storage-as-memory approaches. Lead long-term technology roadmaps, communicate strategy to executives, and mentor engineers while driving R&D.
Location: Texas, Palo Alto
Workplace: Onsite
Employment Type: Full time
Job Function: Hardware, Embedded & Systems Engineering
Seniority: Mid level

Key Responsibilities

  • •Architect the memory/storage hierarchy (DRAM, SSD, and cache layers) for AI workloads.
  • •Define and implement policies for data placement and movement across tiers (hot vs. cold data).
  • •Optimize paging, prefetching, and streaming for AI inference and training.
  • •Partner with software and OS/runtime teams to co-optimize models and data orchestration for maximum AI performance.
  • •Develop long-term technology roadmaps, communicate them to executive staff and partners, and mentor less-experienced engineers.

Pay and Benefits

Salary: USD 190,000 - 274,000 annually
Perks:Health InsuranceDentalVisionDisability InsuranceLife InsuranceParental LeavePaid Leave

Key Requirements

  • •Four-year or graduate degree in Electrical Engineering or a related field, or equivalent work experience.
  • •Typically 12+ years of work experience in electrical design and tools, software packages, hardware architecture, or related work.
  • •Expertise in memory design and hardware architecture for systems involving DRAM, SSD, cache layers, and data hierarchy.
  • •Ability to define policies for data placement and movement across tiers (hot vs. cold data) and optimize paging/prefetching/streaming for AI workloads.
  • •Experience with hardware/software co-optimization for AI performance, including storage-as-memory approaches such as spillover and KV cache strategies.
Experience:12+ yearsAI workloadsElectrical hardware design
Education:Bachelor's in Electrical Engineering
Skills:Effective communicationResults orientationLearning agilityDigital fluencyCustomer centricity
Tech Stack:DRAMSSDCache layersPagingPrefetchingStreamingKV cacheUnified memoryMemory poolingCompressionOS/runtime teamsFPGAMATLABPrinted circuit boardSchematic captureSimulationsSystems design

Company Brief

HP
Designs and manufactures personal computers, printers, and related supplies, as well as provides software, services, and solutions for consumers and enterprises worldwide.
Industry: Hardware Devices
Company Size: Enterprise (1,001+ employees)
Revenue: USD 1B+
Growth: Public Company
Valuation: Public Company (Market Cap in USD)
Funding: IPO / Publicly Listed
Headquarters: Palo Alto, United States
Founded: 1939
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Glassdoor: 3.8
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