Principal Product Engineer – High-Speed IP UCIE

Cadence Design Systems
Seoul
Full timeFunction: Communications, PR & CommunityExperience: 7+ yearsEducation: bachelorsSkills: ["Root cause analysis","Communication","Technical leadership","Ownership","Cross-functional collaboration"]

Lead end-to-end product engineering for high-speed interface IP, focusing on post-sales technical support across UCIE and related PHY/controller subsystems. Drive customer engagements, SoC integration reviews, and complex subsystem issue resolution, from pre-silicon to post-silicon bring-up and deployment. Provide technical leadership for RTL, gate-level simulations, and timing closure, while collaborating with R&D, validation, and applications teams. Mentor engineers and improve integration methods using AI-assisted debugging and analytics.

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Cadence Design Systems
Cadence Design Systems
2 days ago

Principal Product Engineer – High-Speed IP UCIE

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Last checked: 2 hours agoStatus: Live

Job Summary

Lead end-to-end product engineering for high-speed interface IP, focusing on post-sales technical support across UCIE and related PHY/controller subsystems. Drive customer engagements, SoC integration reviews, and complex subsystem issue resolution, from pre-silicon to post-silicon bring-up and deployment. Provide technical leadership for RTL, gate-level simulations, and timing closure, while collaborating with R&D, validation, and applications teams. Mentor engineers and improve integration methods using AI-assisted debugging and analytics.
Location: Seoul
Employment Type: Full time
Job Function: Communications, PR & Community
Seniority: Sr. Director level

Key Responsibilities

  • •Act as the primary product engineering owner for UCIE die-to-die subsystems at the customer level
  • •Lead customer engagements, technical discussions, design reviews, and deployment strategy
  • •Own and drive resolution of complex subsystem integration and implementation issues
  • •Lead SoC integration reviews covering PHY and controller subsystems
  • •Provide technical leadership for RTL, gate-level simulations, and timing closure; lead post-silicon bring-up and debug while collaborating with R&D, validation, and applications teams

Key Requirements

  • •Bachelor’s degree in electrical engineering, computer engineering, or related field with 7+ years of experience; or Master’s with 5+ years; or PhD with relevant experience
  • •Strong experience with high-speed interface IP
  • •Deep understanding of RTL design, gate-level verification, and simulation methodologies
  • •Experience with synthesis, STA, and timing closure; backend knowledge is a plus
  • •Familiarity with DFT methodologies, test flows, and system validation approaches
Experience:7+ yearsHigh-speed interface IPMixed-signalSoC integrationPost-silicon bring-up
Education:Bachelor's in Electrical Engineering, Computer Engineering, or related field
Skills:Root cause analysisCommunicationTechnical leadershipOwnershipCross-functional collaboration
Tech Stack:RTLGate-level simulationsTiming closureSTASynthesisDFTUCIePCIeUSBDPHYEthernetDDRLPDDRGDDRHBM PHYsRTL designGate-level verificationTiming closure strategiesSoC integrationRTL simulations

Company Brief

Cadence Design Systems
Provides electronic design automation (EDA) software, IP, and services for semiconductor and systems companies to design, verify, and implement integrated circuits, systems-on-chip, and electronic systems across industries including communications, automotive, and consumer electronics.
Industry: Developer Tools
Company Size: Enterprise (1,001+ employees)
Revenue: USD 1B+
Growth: Public Company
Valuation: Public Company (Market Cap in USD)
Funding: IPO / Publicly Listed
Headquarters: San Jose, United States
Founded: 1988
Glassdoor
Glassdoor: 3.9
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