Cadence Design Systems

4 weeks ago

Principal AI Forward Deployment Engineer

✓ Verified Job

Canonical indexed version, validated from employer's careers page.

Source: Company careers pageValidated by: Fursa AI

Last checked: 7 hours agoStatus: Live

Job Summary

Lead end-to-end deployment of Cadence AI and agentic solutions into customers' silicon design flows, translating frontend and backend design activities into measurable productivity wins powered by flagship LLMs. Serve as the trusted technical lead to customers, embedding Cadence AI tooling, defining KPIs, and driving ROI from pilot to production across multiple sites.

Location: United States

Workplace: Remote

Employment Type: Full time

Job Function: Data Science & Machine Learning

Seniority: Sr. Manager level

Key Responsibilities

•Lead end-to-end deployment of Cadence AI/LLM-powered solutions into the customer’s silicon design flows from RTL through packaging.
•Architect and tune agentic workflows, prompt strategies, and tool-calling patterns on top of flagship LLMs to automate real EDA tasks and provide design copilots.
•Map customer methodology onto Cadence AI building blocks, identify high-ROI insertion points, and build reference flows for long-term ownership.
•Define and report KPIs (cycle-time reduction, engineer-hours saved, first-pass success) and drive pilot-to-production rollout across business units and sites.
•Serve as the senior technical face to customers, conducting design reviews, readouts, and joint roadmaps, while feeding feedback to Cadence R&D and AI platform teams.

Key Requirements

•BS/MS/PhD in EE, ECE, CS, or related discipline.
•10+ years of hands-on semiconductor / chip design experience including front-end, physical design, CAD/methodology, or production tape-outs.
•Deep fluency with industry EDA flows and pain points; has shipped silicon.
•Proven ability to apply LLMs/AI tools to engineering tasks (agent-based debugging, code/RTL generation, automation, copilots, RAG).
•Excellent customer-facing communication; able to engage with staff RTL engineers, PD methodology leads, and CAD/design-enablement leaders

Experience:10+ yearsSemiconductorEDAAI

Education:Bachelor's

Skills:CommunicationLeadershipProblem-solvingCustomer-facingMentoring

Tech Stack:LLMsClaudeGPTGeminiLlamaQwenRAGEDAP&RRTLSynthesis

Company Brief

Cadence Design Systems

Provides electronic design automation (EDA) software, IP, and services for semiconductor and systems companies to design, verify, and implement integrated circuits, systems-on-chip, and electronic systems across industries including communications, automotive, and consumer electronics.

Industry: Developer Tools

Company Size: Enterprise (1,001+ employees)

Revenue: USD 1B+

Growth: Public Company

Valuation: Public Company (Market Cap in USD)

Funding: IPO / Publicly Listed

Headquarters: San Jose, United States

Founded: 1988

Glassdoor: 3.9

Website LinkedIn Glassdoor

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Cadence Design Systems

4 weeks ago

Principal AI Forward Deployment Engineer

✓ Verified Job

Canonical indexed version, validated from employer's careers page.

Source: Company careers pageValidated by: Fursa AI

Last checked: 7 hours agoStatus: Live

Job Summary

Location: United States

Workplace: Remote

Employment Type: Full time

Job Function: Data Science & Machine Learning

Seniority: Sr. Manager level

Key Responsibilities

•Lead end-to-end deployment of Cadence AI/LLM-powered solutions into the customer’s silicon design flows from RTL through packaging.
•Architect and tune agentic workflows, prompt strategies, and tool-calling patterns on top of flagship LLMs to automate real EDA tasks and provide design copilots.
•Map customer methodology onto Cadence AI building blocks, identify high-ROI insertion points, and build reference flows for long-term ownership.
•Define and report KPIs (cycle-time reduction, engineer-hours saved, first-pass success) and drive pilot-to-production rollout across business units and sites.
•Serve as the senior technical face to customers, conducting design reviews, readouts, and joint roadmaps, while feeding feedback to Cadence R&D and AI platform teams.

Key Requirements

•BS/MS/PhD in EE, ECE, CS, or related discipline.
•10+ years of hands-on semiconductor / chip design experience including front-end, physical design, CAD/methodology, or production tape-outs.
•Deep fluency with industry EDA flows and pain points; has shipped silicon.
•Proven ability to apply LLMs/AI tools to engineering tasks (agent-based debugging, code/RTL generation, automation, copilots, RAG).
•Excellent customer-facing communication; able to engage with staff RTL engineers, PD methodology leads, and CAD/design-enablement leaders

Experience:10+ yearsSemiconductorEDAAI

Education:Bachelor's

Skills:CommunicationLeadershipProblem-solvingCustomer-facingMentoring

Tech Stack:LLMsClaudeGPTGeminiLlamaQwenRAGEDAP&RRTLSynthesis

Company Brief

Cadence Design Systems

Industry: Developer Tools

Company Size: Enterprise (1,001+ employees)

Revenue: USD 1B+

Growth: Public Company

Valuation: Public Company (Market Cap in USD)

Funding: IPO / Publicly Listed

Headquarters: San Jose, United States

Founded: 1988

Glassdoor: 3.9

Website LinkedIn Glassdoor