Physical Design PnR Tile Lead

AMD
Markham
Workplace: OnsiteFull timeCAD 135,800 - 232,800 annuallyFunction: Design (Product/UX/UI/Visual)Education: bachelorsSkills: ["Technical leadership","Communication","Mentorship","Program execution","Root-cause analysis"]

Lead physical place-and-route implementation for complex SoC designs at advanced process nodes. Drive Tile PnR strategy from floorplanning through tapeout, including placement, CTS, routing, timing closure, congestion and IR/EM closure, and signoff readiness. Own execution planning, milestones, risk management, and quality metrics across critical IPs. Mentor Tile PnR engineers, run technical reviews, and partner with CAD and methodology teams to improve tools, flows, and automation.

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FursaFursa
AMD
AMD
6 days ago

Physical Design PnR Tile Lead

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Job Summary

Lead physical place-and-route implementation for complex SoC designs at advanced process nodes. Drive Tile PnR strategy from floorplanning through tapeout, including placement, CTS, routing, timing closure, congestion and IR/EM closure, and signoff readiness. Own execution planning, milestones, risk management, and quality metrics across critical IPs. Mentor Tile PnR engineers, run technical reviews, and partner with CAD and methodology teams to improve tools, flows, and automation.
Location: Markham
Workplace: Onsite
Employment Type: Full time
Job Function: Design (Product/UX/UI/Visual)
Seniority: Sr. Manager level

Key Responsibilities

  • •Lead physical implementation of complex SoC tiles from floorplan through tapeout.
  • •Drive Tile PnR strategy across floorplanning, placement, CTS, routing, timing closure, congestion management, IR/EM closure, and signoff readiness.
  • •Define implementation methodologies and best practices to improve PPA, scalability, and design quality, and make technical decisions impacting schedule and silicon success.
  • •Own execution planning, milestones, risk management, and quality metrics for critical IPs and SoC tiles; coordinate across Design, Timing, CAD, Methodology, Full Chip Floorplan, Power, and Verification.
  • •Mentor and develop Tile PnR engineers; conduct technical reviews and lead training and knowledge-sharing; drive adoption of new implementation methodologies, automation, and AI-enabled solutions.

Pay and Benefits

Salary: CAD 135,800 - 232,800 annually

Key Requirements

  • •BS/MS in Electrical Engineering, Computer Engineering, or a related field.
  • •Industry experience in physical design and demonstrated technical leadership across multiple projects or product families.
  • •Multiple successful tape-outs at advanced technology nodes and experience leading critical tiles or IPs.
  • •Recognized expertise in Tile PnR and physical implementation, including congestion analysis, timing architecture, and power optimization.
  • •Familiarity with ICC2, Fusion Compiler, PrimeTime, RedHawk/Totem, Calibre, and related implementation flows.
Experience:Physical designSoC
Education:Bachelor's in Electrical Engineering, Computer Engineering
Skills:Technical leadershipCommunicationMentorshipProgram executionRoot-cause analysis
Languages:En-us
Tech Stack:ICC2Fusion CompilerPrimeTimeRedHawk/TotemCalibre

Company Brief

AMD
Designs and produces semiconductor products including CPUs, GPUs, and adaptive SoCs for consumer, enterprise, and embedded markets, competing across PCs, data centers, and gaming industries.
Industry: Electronics Manufacturing
Company Size: Enterprise (1,001+ employees)
Revenue: USD 1B+
Growth: Public Company
Valuation: Public Company (Market Cap in USD)
Funding: IPO / Publicly Listed
Headquarters: Santa Clara, United States
Founded: 1969
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Glassdoor: 3.9
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