Intel

1 week ago

Mixed Signal IP Verification Engineer

✓ Verified Job

Canonical indexed version, validated from employer's careers page.

Source: Company careers pageValidated by: Fursa AI

Last checked: Just nowStatus: Live

Job Summary

Deliver pre-silicon functional verification for DDR PHY IP used in Intel SoCs across desktop, laptop, and other products. Own the end-to-end verification flow—test plan creation, testbench architecture, testbench development, simulation and coverage (functional/code), and waveform/debug closure. Automate validation to improve efficiency, analyze results to debug at IP/subsystem/SOC level, and collaborate across digital/analog architects, RTL developers, and physical design teams to meet functional, performance, and power goals.

Location: Bengaluru

Workplace: Hybrid

Employment Type: Full time

Job Function: QA, Test & Release Engineering

Seniority: Mid level

Key Responsibilities

•Own all aspects of the functional verification flow to ensure DDR PHY IP meets specification requirements.
•Create verification artifacts including test plan, testbench architecture, and test benches, then validate design and micro-architectural implementation.
•Automate validation tasks to improve efficiency and maintain/improve functional verification infrastructure and methodology.
•Analyze pre-silicon simulation results and support debugging at IP, subsystem, and SoC levels.
•Collaborate with architects, RTL developers, and physical design teams to improve verification of complex architectural/micro-architectural features and meet functional, performance, and power goals.

Key Requirements

•BS or MS degree with 5-10 years of relevant industry experience in design verification.
•Experience across the validation flow from testbench architecture and test plan creation through verification closure.
•Proficiency with SystemVerilog and OVM/UVM for verification work.
•Hands-on debugging using waveform debug, functional coverage and code coverage, including VCS simulations (NLP/non-NLP) and GLS.
•Ability to multitask in a dynamic environment with teams across different geographies, with solid verbal and written communication skills.

Experience:5-10 years

Education:Master's

Skills:CommunicationDebuggingProblem-solvingMultitasking

Tech Stack:DDR PHYDDRPHYSystem VerilogOVMUVMTestbenchTest planVCSGLSGitPythonPerlWaveform debugFunctional coverageCode coverageRTLVSCodeGitHub CopilotAI

Company Brief

Intel

Designs and manufactures semiconductor chips, processors, and related hardware for PCs, data centers, networking, and embedded applications, while providing software and services to accelerate computing across industries globally.

Industry: Electronics Manufacturing

Company Size: Enterprise (1,001+ employees)

Revenue: USD 1B+

Growth: Public Company

Valuation: Public Company (Market Cap in USD)

Funding: IPO / Publicly Listed

Headquarters: Santa Clara, United States

Founded: 1968

Glassdoor: 3.8

Website LinkedIn Glassdoor

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Intel

1 week ago

Mixed Signal IP Verification Engineer

✓ Verified Job

Canonical indexed version, validated from employer's careers page.

Source: Company careers pageValidated by: Fursa AI

Last checked: Just nowStatus: Live

Job Summary

Location: Bengaluru

Workplace: Hybrid

Employment Type: Full time

Job Function: QA, Test & Release Engineering

Seniority: Mid level

Key Responsibilities

•Own all aspects of the functional verification flow to ensure DDR PHY IP meets specification requirements.
•Create verification artifacts including test plan, testbench architecture, and test benches, then validate design and micro-architectural implementation.
•Automate validation tasks to improve efficiency and maintain/improve functional verification infrastructure and methodology.
•Analyze pre-silicon simulation results and support debugging at IP, subsystem, and SoC levels.
•Collaborate with architects, RTL developers, and physical design teams to improve verification of complex architectural/micro-architectural features and meet functional, performance, and power goals.

Key Requirements

•BS or MS degree with 5-10 years of relevant industry experience in design verification.
•Experience across the validation flow from testbench architecture and test plan creation through verification closure.
•Proficiency with SystemVerilog and OVM/UVM for verification work.
•Hands-on debugging using waveform debug, functional coverage and code coverage, including VCS simulations (NLP/non-NLP) and GLS.
•Ability to multitask in a dynamic environment with teams across different geographies, with solid verbal and written communication skills.

Experience:5-10 years

Education:Master's

Skills:CommunicationDebuggingProblem-solvingMultitasking

Tech Stack:DDR PHYDDRPHYSystem VerilogOVMUVMTestbenchTest planVCSGLSGitPythonPerlWaveform debugFunctional coverageCode coverageRTLVSCodeGitHub CopilotAI

Company Brief

Intel

Industry: Electronics Manufacturing

Company Size: Enterprise (1,001+ employees)

Revenue: USD 1B+

Growth: Public Company

Valuation: Public Company (Market Cap in USD)

Funding: IPO / Publicly Listed

Headquarters: Santa Clara, United States

Founded: 1968

Glassdoor: 3.8

Website LinkedIn Glassdoor