Staff DFx Methodology Architect

AMD
San Jose
Workplace: HybridFull timeUSD 145,600 - 249,600 annuallyFunction: Solutions Engineering & Sales EngineeringEducation: bachelorsSkills: ["Communication","Problem-solving","Leadership","Mentoring","Team-collaboration"]

Lead DFx Architecture definition, RTL implementation, and methodology development for FPGA-SoCs and custom ASICs. Drive timing, power, performance and area, mentor design teams, and collaborate cross-functionally with CAD, verification, and product engineering to ensure DFx IPs meet design targets across the design flow.

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FursaFursa
AMD
AMD
2 months ago

Staff DFx Methodology Architect

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Canonical indexed version, validated from employer's careers page.

Source: Company careers pageValidated by: Fursa AI
Last checked: 13 hours agoStatus: Live

Job Summary

Lead DFx Architecture definition, RTL implementation, and methodology development for FPGA-SoCs and custom ASICs. Drive timing, power, performance and area, mentor design teams, and collaborate cross-functionally with CAD, verification, and product engineering to ensure DFx IPs meet design targets across the design flow.
Location: San Jose
Workplace: Hybrid
Employment Type: Full time
Job Function: Solutions Engineering & Sales Engineering

Key Responsibilities

  • •Define and lead SoC-DFx Architecture, Specifications and development of DFx-IPs
  • •Own DFx Architecture documentation, accounting for interactions with other features, the hardware and the firmware
  • •Implement DFx features in RTL using Verilog/SystemVerilog
  • •Co-own Timing and Design Quality Checks (and waivers) for the DFx-IPs
  • •Work cross functionally with DFx execution and verification teams to enable integration and validation of DFx-IPs in all phases of design implementation flow
  • •Travel:

Pay and Benefits

Salary: USD 145,600 - 249,600 annually

Key Requirements

  • •Experience defining and leading DFx architecture, methodology, and RTL design for FPGA-SoCs or ASICs
  • •Strong expertise in Verilog/SystemVerilog RTL design, timing, and power/area optimization
  • •Proficiency with DFx IPs and related verification/validation processes (DFx testing, timing checks)
  • •Ability to lead design teams, manage schedules, and collaborate across CAD, verification, and product engineering
  • •Excellent communication, presentation and problem-solving skills; hands-on when needed
Experience:SemiconductorDFxRTLASICsVerilogSystemVerilog
Education:Bachelor's
Skills:CommunicationProblem-solvingLeadershipMentoringTeam-collaboration
Languages:English
Tech Stack:VerilogSystemVerilogRTLTessentDFxFPGAASICIPATPGIJTAG

Company Brief

AMD
Designs and produces semiconductor products including CPUs, GPUs, and adaptive SoCs for consumer, enterprise, and embedded markets, competing across PCs, data centers, and gaming industries.
Industry: Electronics Manufacturing
Company Size: Enterprise (1,001+ employees)
Revenue: USD 1B+
Growth: Public Company
Valuation: Public Company (Market Cap in USD)
Funding: IPO / Publicly Listed
Headquarters: Santa Clara, United States
Founded: 1969
Glassdoor
Glassdoor: 3.9
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