Senior FPGA Verification Engineer

Anduril
United States
Workplace: OnsiteFull timeUSD 191,000 - 253,000 annuallyFunction: Hardware, Embedded & Systems EngineeringExperience: 8+ yearsEducation: bachelorsSkills: ["Technical leadership","Planning","Reporting","Continuous improvement"]

Design and execute FPGA/ASIC verification for imaging systems, building verification environments and testbenches to validate RTL blocks using VHDL/SystemVerilog. Own verification test planning, coverage (functional/code), and assertion-based verification, while improving the ASIC/FPGA verification flow. Collaborate with an interdisciplinary team to mature prototypes into products, provide verification leadership, and support ground and flight test readiness.

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FursaFursa
Anduril
Anduril
7 hours ago

Senior FPGA Verification Engineer

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Source: Company careers pageValidated by: Fursa AI
Last checked: 1 hour agoStatus: Live
Reposted: similar role first listed 3 months ago

Job Summary

Design and execute FPGA/ASIC verification for imaging systems, building verification environments and testbenches to validate RTL blocks using VHDL/SystemVerilog. Own verification test planning, coverage (functional/code), and assertion-based verification, while improving the ASIC/FPGA verification flow. Collaborate with an interdisciplinary team to mature prototypes into products, provide verification leadership, and support ground and flight test readiness.
Location: United States
Workplace: Onsite
Employment Type: Full time
Job Function: Hardware, Embedded & Systems Engineering
Seniority: Mid level

Key Responsibilities

  • •Architect and design verification environments using SystemVerilog or OVM/UVM.
  • •Create test plans and test cases, track code coverage and functional coverage, and build verification for RTL blocks.
  • •Develop testbenches for RTL block verification using VHDL or SystemVerilog.
  • •Recommend new tools and practices to continuously improve the ASIC/FPGA verification flow.
  • •Provide technical leadership to project verification teams by breaking down work, planning activities, and reporting status.

Pay and Benefits

Salary: USD 191,000 - 253,000 annually
Equity and Bonus:Equity

Key Requirements

  • •A Bachelor's in Electrical Engineering, Computer Engineering, or a related technical field is typically required.
  • •8+ years developing HDL firmware for FPGA devices.
  • •Proven experience developing and simulating RTL designs using VHDL and/or Verilog in a professional FPGA or ASIC development environment.
  • •Proven ability to design, implement, and execute verification testbenches for RTL blocks using VHDL and/or SystemVerilog.
  • •Experience applying chip-level verification methodologies including constrained-random testing, functional coverage analysis, and assertion-based verification (SystemVerilog).
Experience:8+ years
Education:Bachelor's
Skills:Technical leadershipPlanningReportingContinuous improvement
Tech Stack:SystemVerilogOVMUVMVHDLVerilogGitSubversionUnixLinuxCC++PythonPerlShellQuestaSimSynplifyQuartusVivadoASICFPGA

Eligibility

Security Clearance:Secret

Company Brief

Anduril
Designs and builds advanced defense systems combining autonomous aircraft, sensors, and AI-driven software for military and national security applications, focused on modernizing battlefield capabilities and distributed sensing.
Industry: Defense Technology
Company Size: Enterprise (1,001+ employees)
Growth: Scaleup
Valuation: Unicorn (USD 1B+)
Funding: Series E+
Headquarters: Costa Mesa, United States
Founded: 2017
WebsiteLinkedIn