Senior SoC Physical Layout & Full-Chip Integration Engineer

Intel
Phoenix, Austin
Workplace: HybridFull timeUSD 122,440 - 232,190 annuallyFunction: Solutions Engineering & Sales EngineeringExperience: 1-4 yearsSkills: ["Ownership","Technical decision-making","Communication","Project planning","Problem-solving"]

Drive full-chip physical integration for advanced-node silicon development within Intel Foundry’s Design Technology Platform. Lead floorplanning, tapeout preparation, and physical verification closure (DRC/LVS/DFM and rule compliance), while developing custom layout methodologies and scalable design flows. Partner with Technology Development, PDK, and EDA teams to implement manufacturable solutions, analyze emerging transistor architectures, and build automation using Tcl, Python, or SKILL to improve quality and productivity.

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Intel
Intel
4 days ago

Senior SoC Physical Layout & Full-Chip Integration Engineer

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Source: Company careers pageValidated by: Fursa AI
Last checked: 22 hours agoStatus: Live

Job Summary

Drive full-chip physical integration for advanced-node silicon development within Intel Foundry’s Design Technology Platform. Lead floorplanning, tapeout preparation, and physical verification closure (DRC/LVS/DFM and rule compliance), while developing custom layout methodologies and scalable design flows. Partner with Technology Development, PDK, and EDA teams to implement manufacturable solutions, analyze emerging transistor architectures, and build automation using Tcl, Python, or SKILL to improve quality and productivity.
Location: Phoenix, Austin
Workplace: Hybrid
Employment Type: Full time
Job Function: Solutions Engineering & Sales Engineering
Seniority: Mid level

Key Responsibilities

  • •Lead full-chip floorplanning, physical integration, and tapeout activities for advanced-node silicon development vehicles.
  • •Develop and enhance custom layout methodologies and physical design flows.
  • •Drive physical verification closure, including DRC, LVS, DFM, density, and antenna rule compliance.
  • •Collaborate with Technology Development, PDK, and EDA teams to implement scalable and manufacturable design solutions.
  • •Build automation solutions using Tcl, Python, SKILL (or similar) and coordinate tape-in readiness and database integrity for successful execution.

Pay and Benefits

Salary: USD 122,440 - 232,190 annually
Equity and Bonus:Equity
Perks:Health InsuranceRetirementPaid Leave

Key Requirements

  • •Master’s degree in Electrical Engineering, Computer Engineering, or related field with 4+ years of industry experience, or a PhD with 1+ years of industry experience.
  • •Custom/analog/mixed-signal layout design experience in advanced technology nodes, including FEOL layout rules, transistor-level matching, parasitic layout concepts, and custom silicon structures.
  • •Debugging skills in physical verification (LVS, DRC, and DFM) using verification engines such as Calibre or ICV to resolve complex systemic layout errors.
  • •Experience using Tcl, Python, or SKILL to automate layout creation, checking, and full-chip database manipulation.
  • •Strong ownership, technical decision-making, and communication skills to handle ambiguity and deliver high-quality technical results.
Experience:1-4 yearsSemiconductor foundrySemiconductorsPhysical designEDA automation
Education:
Skills:OwnershipTechnical decision-makingCommunicationProject planningProblem-solving
Tech Stack:TclPythonSKILLCalibreICVCadence VirtuosoDRCLVSDFMFinFETGate-All-Around (GAA)

Company Brief

Intel
Designs and manufactures semiconductor chips, processors, and related hardware for PCs, data centers, networking, and embedded applications, while providing software and services to accelerate computing across industries globally.
Industry: Electronics Manufacturing
Company Size: Enterprise (1,001+ employees)
Revenue: USD 1B+
Growth: Public Company
Valuation: Public Company (Market Cap in USD)
Funding: IPO / Publicly Listed
Headquarters: Santa Clara, United States
Founded: 1968
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Glassdoor: 3.8
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