Principal Design Engineer (Virtual Solution)

Cadence Design Systems
Shanghai
Workplace: OnsiteFull timeFunction: Communications, PR & CommunityExperience: 5-10 yearsEducation: bachelorsSkills: ["SystemVerilog","Verilog","C","C++","Python","Palladium","Protium","FPGA","UVM","Qemu","Gem5"]

Design and develop system-level AVIP solutions for emulation/prototyping platforms, build and integrate accelerated verification IP environments, and develop end-to-end verification flows. Architect scalable, multi-protocol validation across clock domains, optimize performance and emulation efficiency, and drive AI/ML-enabled verification to support customer enablement.

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Cadence Design Systems
Cadence Design Systems
2 months ago

Principal Design Engineer (Virtual Solution)

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Source: Company careers pageValidated by: Fursa AI
Last checked: 10 hours agoStatus: Live

Job Summary

Design and develop system-level AVIP solutions for emulation/prototyping platforms, build and integrate accelerated verification IP environments, and develop end-to-end verification flows. Architect scalable, multi-protocol validation across clock domains, optimize performance and emulation efficiency, and drive AI/ML-enabled verification to support customer enablement.
Location: Shanghai
Workplace: Onsite
Employment Type: Full time
Job Function: Communications, PR & Community

Key Responsibilities

  • •Design and develop system-level AVIP solutions for emulation/prototyping platforms (Palladium, Protium)
  • •Build and integrate Accelerated Verification IP environments for complex SoC and subsystem validation
  • •Develop end-to-end verification flows including AVIP integration, testbench and system modeling, bare-metal/driver-level validation
  • •Architect scalable solutions for multi-protocol system validation across multiple clock domains
  • •Optimize solutions for performance, scalability, and emulation efficiency

Key Requirements

  • •Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or related field with 5-10 years’ experience
  • •Strong expertise in high-speed protocols such as PCIe, CXL, AMBA, UCIe, Ethernet (at least one)
  • •Strong RTL design experience (SystemVerilog / Verilog)
  • •Strong C/C++ development experience for modeling, testbench, or system integration
  • •Solid understanding of System-level verification methodologies and Emulation/acceleration flows
Experience:5-10 yearsSemiconductorEDAVerification
Education:Bachelor's
Skills:SystemVerilogVerilogCC++PythonPalladiumProtiumFPGAUVMQemuGem5
Languages:English
Tech Stack:SystemVerilogVerilogC/C++PythonPalladiumProtiumFPGAUVMQemuGem5

Company Brief

Cadence Design Systems
Provides electronic design automation (EDA) software, IP, and services for semiconductor and systems companies to design, verify, and implement integrated circuits, systems-on-chip, and electronic systems across industries including communications, automotive, and consumer electronics.
Industry: Developer Tools
Company Size: Enterprise (1,001+ employees)
Revenue: USD 1B+
Growth: Public Company
Valuation: Public Company (Market Cap in USD)
Funding: IPO / Publicly Listed
Headquarters: San Jose, United States
Founded: 1988
Glassdoor
Glassdoor: 3.9
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