Principal Design Engineer (Virtual Solution)
Cadence Design Systems
Shanghai
Workplace: OnsiteFull timeFunction: Communications, PR & CommunityExperience: 5-10 yearsEducation: bachelorsSkills: ["SystemVerilog","Verilog","C","C++","Python","Palladium","Protium","FPGA","UVM","Qemu","Gem5"]Design and develop system-level AVIP solutions for emulation/prototyping platforms, build and integrate accelerated verification IP environments, and develop end-to-end verification flows. Architect scalable, multi-protocol validation across clock domains, optimize performance and emulation efficiency, and drive AI/ML-enabled verification to support customer enablement.
