Sr Design Engineering Architect

Cadence Design Systems
Bengaluru
Full timeFunction: Architecture & Urban PlanningExperience: 6-16 yearsEducation: bachelorsSkills: ["Verilog","SystemVerilog","UVM","ARM","PCIe","CXL","IDE"]

Senior RTL design engineer with expertise in PCIe IP development, ARM CPU subsystem architecture, memory IO and cache subsystems. Responsible for RTL design and verification, adding features to PCIe/CXL/IDE/UALink IP, ensuring regression coverage, LINT and CDC compliance, and supporting customers. Based in Bangalore or Noida with 6-16 years of RTL experience and SystemVerilog/UVM usage.

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Cadence Design Systems
Cadence Design Systems
6 months ago

Sr Design Engineering Architect

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Last checked: 7 hours agoStatus: Live

Job Summary

Senior RTL design engineer with expertise in PCIe IP development, ARM CPU subsystem architecture, memory IO and cache subsystems. Responsible for RTL design and verification, adding features to PCIe/CXL/IDE/UALink IP, ensuring regression coverage, LINT and CDC compliance, and supporting customers. Based in Bangalore or Noida with 6-16 years of RTL experience and SystemVerilog/UVM usage.
Location: Bengaluru
Employment Type: Full time
Job Function: Architecture & Urban Planning
Seniority: Sr. Manager level

Key Responsibilities

  • •Lead RTL design and verification tasks for PCIe IP and related subsystems, including ARM CPU subsystem, memory IO and cache
  • •Develop and integrate new features into RTL for PCIe/CXL/IDE/UALink IP solutions
  • •Collaborate with RTL teams to verify customer configurations and ensure regression coverage
  • •Support customers by diagnosing issues and ensuring design is clean for LINT and CDC guidelines
  • •Contribute to IP development efforts and potentially scripting tasks to automate flows

Key Requirements

  • •6-16 years of core RTL Design experience using Verilog
  • •SystemVerilog experience and experience with UVM based environment usage / debugging
  • •Architecture and design of CPU subsystem, including memory subsystem design, IO and cache subsystems
  • •PCIe/CXL/IDE experience is highly desirable; prior experience in implementation of complex protocols is desirable
  • •IP development team experience is an added advantage; scripting knowledge is an advantage
Experience:6-16 yearsVLSIIP developmentSemiconductor
Education:Bachelor's
Skills:VerilogSystemVerilogUVMARMPCIeCXLIDE
Tech Stack:VerilogSystemVerilogUVMPCIeCXLIDEARM

Company Brief

Cadence Design Systems
Provides electronic design automation (EDA) software, IP, and services for semiconductor and systems companies to design, verify, and implement integrated circuits, systems-on-chip, and electronic systems across industries including communications, automotive, and consumer electronics.
Industry: Developer Tools
Company Size: Enterprise (1,001+ employees)
Revenue: USD 1B+
Growth: Public Company
Valuation: Public Company (Market Cap in USD)
Funding: IPO / Publicly Listed
Headquarters: San Jose, United States
Founded: 1988
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