Lead RTL Design Engineer

AMD
Bengaluru
Workplace: OnsiteFull timeFunction: Design (Product/UX/UI/Visual)Experience: 8+ yearsEducation: bachelorsSkills: ["Self-driven","Independent","Communication","Problem-solving"]

Own SoC-level RTL design and integration in AMD’s SoC Design team, coordinating with IP development, verification, front-end integration, and physical design across the SoC lifecycle. You’ll integrate third-party and internal IPs (including voltage/clock/reset/fuse/I/O aspects), implement SoC power, perform static verification (RTL lint, CDC/RDC, power/connectivity checks), and debug multi-IP simulation and integration issues while leading a design domain (e.g., integration, power, CDC/RDC, connectivity).

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FursaFursa
AMD
AMD
1 month ago

Lead RTL Design Engineer

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Source: Company careers pageValidated by: Fursa AI
Last checked: 6 hours agoStatus: Live

Job Summary

Own SoC-level RTL design and integration in AMD’s SoC Design team, coordinating with IP development, verification, front-end integration, and physical design across the SoC lifecycle. You’ll integrate third-party and internal IPs (including voltage/clock/reset/fuse/I/O aspects), implement SoC power, perform static verification (RTL lint, CDC/RDC, power/connectivity checks), and debug multi-IP simulation and integration issues while leading a design domain (e.g., integration, power, CDC/RDC, connectivity).
Location: Bengaluru
Workplace: Onsite
Employment Type: Full time
Job Function: Design (Product/UX/UI/Visual)
Seniority: Mid level

Key Responsibilities

  • •Deliver SoC-level design and integration work.
  • •Integrate IPs and SoC fabric elements including voltage/clock/reset crossings, fuses, and I/O.
  • •Develop RTL design and code for SoC logic and features.
  • •Execute SoC power design and power implementation activities.
  • •Run static verification (RTL lint, CDC/RDC, power checks, connectivity checks) and debug multi-IP simulation/integration issues with verification teams; support top-level synthesis and full-chip implementation, leading a design domain.

Key Requirements

  • •8+ years of SoC design and Verilog RTL development experience.
  • •Verilog RTL development for CPU/SoC/ASIC environments.
  • •Strong understanding of SoC integration and SoC architecture, including system interconnect protocols such as AXI and PCIe.
  • •Experience with UPF and low-power methodologies, static timing analysis (STA), and physical design interaction/implementation.
  • •Familiarity with scripting languages such as Tcl, Perl, Ruby, or Shell, plus knowledge of formal verification techniques and tools.
Experience:8+ yearsSoC designVerilog RTLASIC
Education:Bachelor's in ECE/EEE
Skills:Self-drivenIndependentCommunicationProblem-solving
Languages:En-us
Tech Stack:VerilogRTLSoCASICAXIPCIeUPFLow-powerStatic timing analysis (STA)TclPerlRubyShellCDCRDCStatic verification

Company Brief

AMD
Designs and produces semiconductor products including CPUs, GPUs, and adaptive SoCs for consumer, enterprise, and embedded markets, competing across PCs, data centers, and gaming industries.
Industry: Electronics Manufacturing
Company Size: Enterprise (1,001+ employees)
Revenue: USD 1B+
Growth: Public Company
Valuation: Public Company (Market Cap in USD)
Funding: IPO / Publicly Listed
Headquarters: Santa Clara, United States
Founded: 1969
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Glassdoor: 3.9
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