Lead Design Engineer

Cadence Design Systems
Hyderabad
Workplace: OnsiteFull timeFunction: Design (Product/UX/UI/Visual)Experience: 5+ yearsEducation: bachelorsSkills: ["Leadership","Communication","Analytical problem solving","Problem solving","Self-motivated team player"]

Develop, automate, and maintain EDA flows and scripts for physical implementation, including TFM to optimize PPA for IPs and soft controllers. Characterize and optimize PPA-focused flows for performance and power across advanced process nodes (TSMC, Intel, Samsung, Rapidus Foundries). Lead regression infrastructure for RTL/flow quality tracking and PPA monitoring, and drive digital design implementation using Cadence backend tools. Use AI-driven automation to advance full-chip floorplanning and partitioning.

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FursaFursa
Cadence Design Systems
Cadence Design Systems
1 month ago

Lead Design Engineer

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Source: Company careers pageValidated by: Fursa AI
Last checked: 10 hours agoStatus: Live
Reposted: similar role first listed 5 months ago

Job Summary

Develop, automate, and maintain EDA flows and scripts for physical implementation, including TFM to optimize PPA for IPs and soft controllers. Characterize and optimize PPA-focused flows for performance and power across advanced process nodes (TSMC, Intel, Samsung, Rapidus Foundries). Lead regression infrastructure for RTL/flow quality tracking and PPA monitoring, and drive digital design implementation using Cadence backend tools. Use AI-driven automation to advance full-chip floorplanning and partitioning.
Location: Hyderabad
Workplace: Onsite
Employment Type: Full time
Job Function: Design (Product/UX/UI/Visual)

Key Responsibilities

  • •Develop, automate, and maintain EDA flows and scripts for physical implementation.
  • •Develop TFM to optimize PPA for IPs and soft controllers.
  • •Perform PPA characterization and optimize flows for performance- and power-oriented results in advanced process nodes.
  • •Manage regression infrastructure to track RTL/flow quality and PPA of key designs.
  • •Implement digital design using Cadence EDA tools and automate full-chip floorplanning/partitioning with AI-based approaches.

Key Requirements

  • •MS/MTech/BE/BTech in Electronics with 5+ years' experience.
  • •Physical design experience in an ASIC design environment.
  • •Knowledge of the complete ASIC design flow: synthesis, physical design, timing analysis, power analysis, and formal verification.
  • •Expertise in high-frequency design methodologies for ASIC backend flows.
  • •Solid scripting skills (Python and Tcl) and strong leadership, communication, analytical, and problem-solving skills.
Experience:5+ yearsASIC designEDAPhysical designSoC/Full chip floorplanning
Education:Bachelor's in Electronics
Skills:LeadershipCommunicationAnalytical problem solvingProblem solvingSelf-motivated team player
Tech Stack:Cadence EDAGenusInnovusConformalLitmusTempusVoltusCertusPegasusTSMCIntelSamsungRapidus FoundriesPythonTclAI

Company Brief

Cadence Design Systems
Provides electronic design automation (EDA) software, IP, and services for semiconductor and systems companies to design, verify, and implement integrated circuits, systems-on-chip, and electronic systems across industries including communications, automotive, and consumer electronics.
Industry: Developer Tools
Company Size: Enterprise (1,001+ employees)
Revenue: USD 1B+
Growth: Public Company
Valuation: Public Company (Market Cap in USD)
Funding: IPO / Publicly Listed
Headquarters: San Jose, United States
Founded: 1988
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