Senior DFT ATPG Lead

DFx silicon design engineer role within AMD’s S3 SOC DFX team. You will own and lead DFX design architecture, implement features such as SCAN, ATPG, MBIST, and BSCAN, collaborate with IP design teams, RTL/PD groups, and Synthesis to ensure correct DFT implementation and timing closure, and provide post-silicon support for bring-up.