ASIC Engineering Digital Designer/ Leader ( digital design, FSM, CPU sub-systems, complex SOCs, FPGA validation | 8-12 Years | Pune)
Cisco
Pune
Workplace: OnsiteFull timeFunction: Design (Product/UX/UI/Visual)Experience: 8-12 yearsEducation: mastersSkills: ["SystemVerilog","RTL","DFT","Synthesis","Verification","ASIC/SoC design","FPGA","CPU subsystems","HDL","Timing","Power","EDA tooling","GDS2","Tapeout"]Lead digital design for silicon photonics ASICs, managing RTL design of CPU sub-systems and data paths through tapeout and post-silicon support. Collaborate with cross-functional teams across firmware, packaging, and process engineering to optimize power, performance, and manufacturability for high-speed 100G-400G interconnects in Cisco's Client Optics Group.
