ASIC Engineering Digital Designer/ Leader ( digital design, FSM, CPU sub-systems, complex SOCs, FPGA validation | 8-12 Years | Pune)

Cisco
Pune
Workplace: OnsiteFull timeFunction: Software EngineeringExperience: 8-12 yearsEducation: bachelorsSkills: ["Technical leadership","Collaboration","Communication","Analytical thinking","Problem-solving"]

Lead digital design for silicon photonics in Cisco’s Client Optics Group, driving the ASIC lifecycle from architecture and RTL design of CPU subsystems through tapeout and post-silicon support. Own block and top-level design, block-level verification, and integration for high-speed optical interconnects (100G/200G/400G). Collaborate with cross-functional teams across verification, firmware, packaging, and process engineering to ensure functional closure, tape-out readiness, and successful FPGA prototyping and lab validation.

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Cisco
Cisco
3 months ago

ASIC Engineering Digital Designer/ Leader ( digital design, FSM, CPU sub-systems, complex SOCs, FPGA validation | 8-12 Years | Pune)

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Source: Company careers pageValidated by: Fursa AI
Last checked: 14 hours agoStatus: Closed
Reposted: similar role first listed 1 month ago

Job Summary

Lead digital design for silicon photonics in Cisco’s Client Optics Group, driving the ASIC lifecycle from architecture and RTL design of CPU subsystems through tapeout and post-silicon support. Own block and top-level design, block-level verification, and integration for high-speed optical interconnects (100G/200G/400G). Collaborate with cross-functional teams across verification, firmware, packaging, and process engineering to ensure functional closure, tape-out readiness, and successful FPGA prototyping and lab validation.
Location: Pune
Workplace: Onsite
Employment Type: Full time
Job Function: Software Engineering
Seniority: Mid level

Key Responsibilities

  • •Provide technical leadership for digital logic development for silicon photonics and high-performance optical interconnects (100G/200G/400G).
  • •Manage end-to-end ASIC lifecycle including architectural conception, RTL-based design of CPU subsystems and data-path interfaces, tapeout, and post-silicon production support.
  • •Design complex digital blocks and CPU subsystems; propagate top-level specs to block-level specs for high-speed datapaths and low-speed control planes including timing and power budgets.
  • •Independently simulate, verify, debug, and support verification coverage sign-off; support integration and verification of SerDes and DSP IP.
  • •Support backend activities such as synthesis, timing closure, DFT, and low power design, including design automation scripts and QOR metric processing; contribute to FPGA prototyping and validation.

Key Requirements

  • •Bachelor’s or master’s degree in electrical engineering, Electronics Engineering, or related field (master’s strongly preferred).
  • •8–12 years of hands-on digital design experience covering FSM and CPU sub-systems, complex SoCs, and FPGA validation.
  • •Strong knowledge of ASIC/SoC design flow including RTL development (SystemVerilog), simulation, lint, CDC/RDC, synthesis, formal/equivalence checking, DFT, and implementation handoff.
  • •Experience with full front-end design and backend tool exposure including CDC, synthesis, LEC, and DFT.
  • •Familiarity with protocols and interfaces such as SPI, I2C, APB, and AXI, plus high-speed SerDes, Ethernet, and D2D PHY IP.
Experience:8-12 yearsSilicon photonicsOptical interconnectsASIC/SoC designFPGA validation
Education:Bachelor's in Electrical engineering, Electronics Engineering, or related field
Skills:Technical leadershipCollaborationCommunicationAnalytical thinkingProblem-solving
Tech Stack:Digital designASICSoCFSMCPU subsystemsFPGA validationSystemVerilogRTLSimulationLintCDC/RDCSynthesisFormal/equivalence checkingDFTPhysical designGDS2VerificationLECCDCLow power design

Company Brief

Cisco
Global technology company that designs, manufactures, and sells networking hardware, telecommunications equipment, and high-technology services and products for enterprises, service providers, and governments worldwide.
Industry: Networking Equipment
Company Size: Enterprise (1,001+ employees)
Revenue: USD 1B+
Growth: Public Company
Valuation: Public Company (Market Cap in USD)
Funding: IPO / Publicly Listed
Headquarters: San Jose, United States
Founded: 1984
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Glassdoor: 4.0
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