ASIC Engineering Digital Designer/ Leader ( digital design, FSM, CPU sub-systems, complex SOCs, FPGA validation | 8-12 Years | Pune)
Lead digital design for silicon photonics in Cisco’s Client Optics Group, driving the ASIC lifecycle from architecture and RTL design of CPU subsystems through tapeout and post-silicon support. Own block and top-level design, block-level verification, and integration for high-speed optical interconnects (100G/200G/400G). Collaborate with cross-functional teams across verification, firmware, packaging, and process engineering to ensure functional closure, tape-out readiness, and successful FPGA prototyping and lab validation.
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