1 day ago

Silicon Design Engineer

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Last checked: 7 hours agoStatus: Live

Job Summary

Design and verify advanced silicon testchips for FPGA and ASIC solutions within AMD’s AECG Silicon Integration & Test team. Own the RTL-to-GDS physical implementation flow, including synthesis, floorplanning, placement, CTS, routing, timing closure, physical verification, and design signoff through GDSII tapeout readiness. Validate SoC timing using STA (e.g., PrimeTime), perform physical signoff (IR drop, EM, noise, DRC/LVS), and support post-silicon bring-up and lab-based validation.

Location: San Jose

Workplace: Onsite

Employment Type: Full time

Job Function: Design (Product/UX/UI/Visual)

Key Responsibilities

•Drive the timing-aware/physical-aware synthesis flow to generate optimized netlists using tools like Design Compiler.
•Lead the end-to-end digital ASIC/SoC physical design cycle from RTL handoff through GDSII tapeout, including floorplanning, power planning, placement, CTS, routing, timing closure, physical verification, and design signoff.
•Close SoC timing using STA (e.g., PrimeTime) to validate setup/hold margins across PVT corners.
•Perform physical signoff analyses (IR drop, electromigration, noise, DRC/LVS) and support cross-functional reviews to ensure tapeout readiness.
•Assist with post-silicon bring-up, debugging, and lab-based validation activities.

Pay and Benefits

Salary: USD 145,600 - 249,600 annually

Key Requirements

•Strong RTL-to-GDS physical implementation experience across the ASIC/SoC flow, including synthesis, floorplanning, power planning, placement, CTS, routing, timing closure, and physical signoff.
•Hands-on ability to drive SoC timing closure using Static Timing Analysis (STA) and validate setup/hold margins across PVT corners.
•Experience with physical signoff methodologies such as IR drop, electromigration (EM), noise analysis, and DRC/LVS verification, plus tapeout qualification.
•Strong understanding of CMOS fundamentals, semiconductor device physics, signal integrity, power integrity, and device reliability mechanisms.
•Advanced degree in electrical & electronics engineering or physical sciences (PhD/MS) preferred, or a bachelor’s degree with relevant industry experience.

Experience:ASIC designSoC designSemiconductorPhysical designTapeoutSilicon validation

Education:Master's in Electrical & electronics engineering or physical sciences

Skills:Independent workCross-functional collaborationAnalytical thinkingProblem-solvingDriving to closure

Languages:English

Tech Stack:RTL-to-GDSGDSIIASIC/SoCFPGAPlace-and-routeTiming closurePhysical verificationDesign signoffTapeout readinessStatic Timing Analysis (STA)PrimeTimeDesign CompilerCadence GenusCadence InnovusSynopsys Fusion CompilerFloorplanningPower planningPlacementClock tree synthesis (CTS)Routing

Eligibility

Work Authorization:Authorization required. Sponsorship not provided.

Company Brief

AMD

Designs and produces semiconductor products including CPUs, GPUs, and adaptive SoCs for consumer, enterprise, and embedded markets, competing across PCs, data centers, and gaming industries.

Industry: Electronics Manufacturing

Company Size: Enterprise (1,001+ employees)

Revenue: USD 1B+

Growth: Public Company

Valuation: Public Company (Market Cap in USD)

Funding: IPO / Publicly Listed

Headquarters: Santa Clara, United States

Founded: 1969

Glassdoor: 3.9

Website LinkedIn

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AMD