Principal Design Engineer

Cadence Design Systems
India
Workplace: OnsiteFull timeFunction: Design (Product/UX/UI/Visual)Experience: 7+ yearsEducation: bachelorsSkills: []

Senior-level hardware verification engineer responsible for leading design verification efforts for complex electronic designs. Requires 7+ years of SV/UVM-based verification, strong fundamentals in functional verification, environment planning, test plan generation, and hands-on SystemVerilog/UVM coding to develop verification environments and drive projects from concept to verification closure. Experience with memory IP verification is a plus.

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Cadence Design Systems
Cadence Design Systems
6 months ago

Principal Design Engineer

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Canonical indexed version, validated from employer's careers page.

Source: Company careers pageValidated by: Fursa AI
Last checked: 18 hours agoStatus: Live
Reposted: similar role first listed 8 months ago

Job Summary

Senior-level hardware verification engineer responsible for leading design verification efforts for complex electronic designs. Requires 7+ years of SV/UVM-based verification, strong fundamentals in functional verification, environment planning, test plan generation, and hands-on SystemVerilog/UVM coding to develop verification environments and drive projects from concept to verification closure. Experience with memory IP verification is a plus.
Location: India
Workplace: Onsite
Employment Type: Full time
Job Function: Design (Product/UX/UI/Visual)

Key Responsibilities

  • •Lead design verification for complex designs from concept to verification closure.
  • •Develop and maintain functional verification environments and test plans.
  • •Plan and execute verification strategies using SV/UVM, including environment development and coverage closure.
  • •Collaborate with IP verification, especially memory IP (DDR/HBM/GDDR) when applicable.
  • •Mentor and guide junior engineers in verification methodologies and coding practices.

Key Requirements

  • •BE/BTech/ME/MTech - Electrical / Electronics / VLSI with an experience as a design and verification engineer.
  • •7+ years of Design Verification experience with SV/UVM.
  • •Strong background on functional verification fundamentals, environment planning, test plan generation, environment development is a must.
  • •Design Verification experience verifying complex designs and leading projects from concept to verification closure.
  • •Strong hands-on UVM and SystemVerilog coding experience and functional verification environment development is required.
Experience:7+ yearsVLSIHardware designVerificationUVMSystemVerilog
Education:Bachelor's in Electrical / Electronics / VLSI
Tech Stack:SystemVerilogUVMVerilogDDRHBMGDDR

Company Brief

Cadence Design Systems
Provides electronic design automation (EDA) software, IP, and services for semiconductor and systems companies to design, verify, and implement integrated circuits, systems-on-chip, and electronic systems across industries including communications, automotive, and consumer electronics.
Industry: Developer Tools
Company Size: Enterprise (1,001+ employees)
Revenue: USD 1B+
Growth: Public Company
Valuation: Public Company (Market Cap in USD)
Funding: IPO / Publicly Listed
Headquarters: San Jose, United States
Founded: 1988
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