CPU Physical Design Engineer

Intel
Austin
Workplace: OnsiteFull timeUSD 105,650 - 200,340 annuallyFunction: Design (Product/UX/UI/Visual)Experience: 3+ yearsEducation: bachelorsSkills: ["Collaboration","Analysis","Problem-solving"]

Design and implement custom CPU physical layouts within Intel’s CPU development team, taking designs from RTL through GDS and into a manufacturing-ready database. Own the end-to-end physical design flow—synthesis, place & route, clock tree synthesis, floorplanning, static timing, and power/clock distribution—then perform verification and signoff including formal equivalence, DRC/LVS, and reliability, coordinating closely with logic, circuit, architecture, and automation teams.

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FursaFursa
Intel
Intel
4 days ago

CPU Physical Design Engineer

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Last checked: 6 hours agoStatus: Live
Reposted: similar role first listed 6 months ago

Job Summary

Design and implement custom CPU physical layouts within Intel’s CPU development team, taking designs from RTL through GDS and into a manufacturing-ready database. Own the end-to-end physical design flow—synthesis, place & route, clock tree synthesis, floorplanning, static timing, and power/clock distribution—then perform verification and signoff including formal equivalence, DRC/LVS, and reliability, coordinating closely with logic, circuit, architecture, and automation teams.
Location: Austin
Workplace: Onsite
Employment Type: Full time
Job Function: Design (Product/UX/UI/Visual)

Key Responsibilities

  • •Perform physical design implementation of custom CPU designs from RTL to GDS to produce a manufacturing-ready design database.
  • •Execute the CPU physical design flow including synthesis, place and route, clock tree synthesis, floorplanning, static timing, and power/clock distribution.
  • •Conduct verification and signoff such as formal equivalence, static timing, reliability verification, power integrity, DRC/LVS, noise flow, and structural design checking with actionable recommendations.
  • •Apply CPU physical design expertise across areas like physical clock design, timing closure, structured placement/routing, multi-power-domain analysis, synthesis, and DFT.
  • •Partner with industry EDA vendors to build and enhance tool capabilities and optimize CPU design for power, frequency, and area while improving physical design methodologies and flow automation.

Pay and Benefits

Salary: USD 105,650 - 200,340 annually
Perks:Health InsuranceRetirementPaid LeaveEquity

Key Requirements

  • •B.S. in Computer Engineering, Electrical Engineering, or related field with 3+ years of relevant experience, or M.S. with 2+ years (or higher degree).
  • •2+ years of experience in synthesis of a digital logic block or partition.
  • •2+ years’ experience with integrated circuit design tools (e.g., Synopsys/Cadence) including logic synthesis, place and route, static timing analysis, and design closure.
  • •2+ years’ experience with PV convergence (such as static timing and power analysis).
  • •2+ years’ experience in CPU physical design verification including formal equivalence, electrical rules, DRC/LVS, and noise flow; plus TCL scripting.
Experience:3+ years
Education:Bachelor's in Computer Engineering or Electrical Engineering (or related field)
Skills:CollaborationAnalysisProblem-solving
Tech Stack:SynopsysCadenceTCLRTL to GDSSynthesisPlace and routeStatic timing analysisClock tree synthesisFloor planningPower/clock distributionFormal equivalence verificationPV convergencePower integrityNoise analysisDRC/LVSElectrical rule checkingDFT

Company Brief

Intel
Designs and manufactures semiconductor chips, processors, and related hardware for PCs, data centers, networking, and embedded applications, while providing software and services to accelerate computing across industries globally.
Industry: Electronics Manufacturing
Company Size: Enterprise (1,001+ employees)
Revenue: USD 1B+
Growth: Public Company
Valuation: Public Company (Market Cap in USD)
Funding: IPO / Publicly Listed
Headquarters: Santa Clara, United States
Founded: 1968
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