Lead Design Engineer(Virtual Solution)

Cadence Design Systems
Shanghai
Workplace: OnsiteFull timeFunction: Design (Product/UX/UI/Visual)Experience: 3+ yearsEducation: bachelorsSkills: ["SystemVerilog","Verilog","C++","Python","C","SV","UVM"]

Design and verify system-level AVIP solutions for emulation and prototyping platforms (Palladium/Protium), build and integrate verification environments, and develop end-to-end flows. Collaborate with cross-functional teams to debug, optimize performance, and enable customer bring-up and deployment of advanced verification solutions in a high-speed, multi-language ecosystem.

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Cadence Design Systems
Cadence Design Systems
3 months ago

Lead Design Engineer(Virtual Solution)

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Source: Company careers pageValidated by: Fursa AI
Last checked: 5 hours agoStatus: Live

Job Summary

Design and verify system-level AVIP solutions for emulation and prototyping platforms (Palladium/Protium), build and integrate verification environments, and develop end-to-end flows. Collaborate with cross-functional teams to debug, optimize performance, and enable customer bring-up and deployment of advanced verification solutions in a high-speed, multi-language ecosystem.
Location: Shanghai
Workplace: Onsite
Employment Type: Full time
Job Function: Design (Product/UX/UI/Visual)

Key Responsibilities

  • •Design and develop system-level AVIP solutions for emulation/prototyping platforms (Palladium, Protium)
  • •Build and integrate Accelerated Verification IP environments for complex SoC and subsystem validation
  • •Develop end-to-end verification flows including: AVIP integration, testbench and system modeling, bare-metal / driver-level validation
  • •Optimize solutions for performance, scalability, and emulation efficiency
  • •Develop custom test cases, tools, and automation to enable advanced use models (embedded / co-emulation / hybrid flows)

Key Requirements

  • •Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or related field with at least 3 years’ experience
  • •Strong expertise in high-speed protocols such as: PCIe, CXL, AMBA, UCIe, Ethernet (at least one)
  • •RTL design experience (SystemVerilog / Verilog)
  • •C/C++ development experience for modeling, testbench, or system integration
  • •Hands-on experience with Palladium / Protium / FPGA / emulation platforms is strongly preferred
Experience:3+ yearsSemiconductorsEDAEmbeddedVerificationFPGAEmulation
Education:Bachelor's
Skills:SystemVerilogVerilogC++PythonCSVUVM
Languages:English
Tech Stack:PalladiumProtiumFPGAEmulationPCIeCXLAMBAUCIeVerilogSystemVerilogC/C++PythonTestbenchAI/ML (verification related)

Company Brief

Cadence Design Systems
Provides electronic design automation (EDA) software, IP, and services for semiconductor and systems companies to design, verify, and implement integrated circuits, systems-on-chip, and electronic systems across industries including communications, automotive, and consumer electronics.
Industry: Developer Tools
Company Size: Enterprise (1,001+ employees)
Revenue: USD 1B+
Growth: Public Company
Valuation: Public Company (Market Cap in USD)
Funding: IPO / Publicly Listed
Headquarters: San Jose, United States
Founded: 1988
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Glassdoor: 3.9
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