Lead Design Engineer(Virtual Solution)
Cadence Design Systems
Shanghai
Workplace: OnsiteFull timeFunction: Design (Product/UX/UI/Visual)Experience: 3+ yearsEducation: bachelorsSkills: ["SystemVerilog","Verilog","C++","Python","C","SV","UVM"]Design and verify system-level AVIP solutions for emulation and prototyping platforms (Palladium/Protium), build and integrate verification environments, and develop end-to-end flows. Collaborate with cross-functional teams to debug, optimize performance, and enable customer bring-up and deployment of advanced verification solutions in a high-speed, multi-language ecosystem.
