SR ENGINEER, DDEG DESMETH DFT
Hyderabad
Workplace: OnsiteFull timeFunction: QA, Test & Release EngineeringSkills: []Develop verification infrastructure and environments for probe and burn DFT test modes, including porting DFT patterns into the verification flow. Support DRAM and emerging memory design teams by simulating, analyzing, and debugging pre-silicon full-chip and block-level designs. Create SystemVerilog testbench infrastructure with UVM and constrained-random verification, run regressions, close coverage, automate simulation data collection, and maintain in-house verification tools and vectors.
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