[Closed] Design Engineering Architect at Cadence Design Systems (Seoul)

This position is no longer accepting applications.

Cadence Design Systems

1 day ago

Design Engineering Architect

✓ Verified Job

Canonical indexed version, validated from employer's careers page.

Source: Company careers pageValidated by: Fursa AI

Last checked: 42 minutes agoStatus: Closed

Job Summary

Drive customer engagements across multiple IP product lines by applying deep expertise in IP design and verification for SerDes and ADCs. Lead and contribute to high-speed I/O IC design for CMOS SerDes standards, jitter, and signal equalization, including key blocks such as driver/receiver, serializer/deserializer, PLL, clock distribution, and bias/bandgap and voltage regulators. Communicate technical requirements and impacts clearly and solve complex issues independently.

Location: Seoul

Workplace: Onsite

Employment Type: Full time

Job Function: Hardware, Embedded & Systems Engineering

Seniority: Mid level

Key Responsibilities

•Drive customer engagements for multiple IP product lines with customer-specific features.
•Apply expertise in IP design and verification for SerDes and ADC solutions.
•Use knowledge of SerDes standards, jitter, and signal equalization to support customer requirements.
•Architect and contribute to design of key SerDes circuit blocks and ADC designs.
•Communicate technical requirements and the impact of issues or program directions at the customer engagement level, and resolve issues independently.

Key Requirements

•Strong technical background in IP design and verification with experience in a direct customer-facing role.
•18-20 years of experience designing and developing CMOS SerDes, ADC, or high-speed I/O ICs.
•Working knowledge of common SerDes standards and their electrical characteristics.
•Thorough understanding of jitter and signal equalization techniques.
•Design experience across SerDes circuit blocks (e.g., driver/receiver, serializer/deserializer, phase interpolator, low-jitter PLL, clock distribution, bias/bandgap, voltage regulators) and proficiency with ADC architectures.

Experience:18-20 years

Skills:Problem-solvingCommunicationTeamworkAnalog aptitudeTechnical communication

Tech Stack:IP designIP verificationCMOS SerDesADCHigh-speed I/OSerDes standardsJitterSignal equalizationDriverReceiverSerializerDeserializerPhase InterpolatorLow jitter PLLHigh Speed Clock DistributionBias and BandgapVoltage Regulators

Company Brief

Cadence Design Systems

Provides electronic design automation (EDA) software, IP, and services for semiconductor and systems companies to design, verify, and implement integrated circuits, systems-on-chip, and electronic systems across industries including communications, automotive, and consumer electronics.

Industry: Developer Tools

Company Size: Enterprise (1,001+ employees)

Revenue: USD 1B+

Growth: Public Company

Valuation: Public Company (Market Cap in USD)

Funding: IPO / Publicly Listed

Headquarters: San Jose, United States

Founded: 1988

Glassdoor: 3.9

Website LinkedIn Glassdoor

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This position is no longer accepting applications.

Cadence Design Systems

1 day ago

Design Engineering Architect

✓ Verified Job

Canonical indexed version, validated from employer's careers page.

Source: Company careers pageValidated by: Fursa AI

Last checked: 42 minutes agoStatus: Closed

Job Summary

Location: Seoul

Workplace: Onsite

Employment Type: Full time

Job Function: Hardware, Embedded & Systems Engineering

Seniority: Mid level

Key Responsibilities

•Drive customer engagements for multiple IP product lines with customer-specific features.
•Apply expertise in IP design and verification for SerDes and ADC solutions.
•Use knowledge of SerDes standards, jitter, and signal equalization to support customer requirements.
•Architect and contribute to design of key SerDes circuit blocks and ADC designs.
•Communicate technical requirements and the impact of issues or program directions at the customer engagement level, and resolve issues independently.

Key Requirements

•Strong technical background in IP design and verification with experience in a direct customer-facing role.
•18-20 years of experience designing and developing CMOS SerDes, ADC, or high-speed I/O ICs.
•Working knowledge of common SerDes standards and their electrical characteristics.
•Thorough understanding of jitter and signal equalization techniques.
•Design experience across SerDes circuit blocks (e.g., driver/receiver, serializer/deserializer, phase interpolator, low-jitter PLL, clock distribution, bias/bandgap, voltage regulators) and proficiency with ADC architectures.

Experience:18-20 years

Skills:Problem-solvingCommunicationTeamworkAnalog aptitudeTechnical communication

Company Brief

Cadence Design Systems

Industry: Developer Tools

Company Size: Enterprise (1,001+ employees)

Revenue: USD 1B+

Growth: Public Company

Valuation: Public Company (Market Cap in USD)

Funding: IPO / Publicly Listed

Headquarters: San Jose, United States

Founded: 1988

Glassdoor: 3.9

Website LinkedIn Glassdoor