Physical Design Engineer (Full-Chip / SoC-Level) - Singapore

ByteDance
Singapore
Workplace: OnsiteFull timeFunction: Design (Product/UX/UI/Visual)Experience: 5+ yearsEducation: bachelorsSkills: []

Own full-chip/SoC physical design from early planning through final GDS/tapeout. Define chip-level physical design strategy (die size, utilization, floorplanning), drive block partitioning and pin/bump planning, and design clock architecture. Establish hierarchical implementation methodology and drive convergence across physical-design blocks and subsystems, supporting tape-out, mass production, packaging, testing, and board-level verification.

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FursaFursa
ByteDance
ByteDance
14 hours ago

Physical Design Engineer (Full-Chip / SoC-Level) - Singapore

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Source: Company careers pageValidated by: Fursa AI
Last checked: 14 hours agoStatus: Live

Job Summary

Own full-chip/SoC physical design from early planning through final GDS/tapeout. Define chip-level physical design strategy (die size, utilization, floorplanning), drive block partitioning and pin/bump planning, and design clock architecture. Establish hierarchical implementation methodology and drive convergence across physical-design blocks and subsystems, supporting tape-out, mass production, packaging, testing, and board-level verification.
Location: Singapore
Workplace: Onsite
Employment Type: Full time
Job Function: Design (Product/UX/UI/Visual)
Seniority: Mid level

Key Responsibilities

  • •Own the full chip / SoC from early physical planning through final GDS/tapeout.
  • •Define chip-level physical design strategy, including die size, utilization targets, and floorplanning.
  • •Drive block partitioning, pin/bump planning, and clock architecture design.
  • •Establish hierarchical implementation methodology.
  • •Drive convergence across all physical-design blocks and subsystems.

Key Requirements

  • •BS degree in Electrical Engineering, Computer Engineering, or equivalent practical experience.
  • •5+ years of experience in physical design / physical implementation.
  • •Experience owning full chip / SoC physical implementation from planning to tapeout.
  • •Hands-on experience with industry-standard PD tools, e.g., Synopsys ICC2 and Cadence Innovus.
  • •Experience with chip-level floorplanning, clock architecture, and hierarchical methodology.
Experience:5+ years
Education:Bachelor's
Tech Stack:Synopsys ICC2Cadence InnovusLogic SynthesisDesign for Testability (DFT)Static Timing Analysis (STA)Physical and STA SignoffPower IntegrityIR dropElectromagnetic Compatibility (EMC)GDSFloorplanningClock architectureHierarchical methodologyTape-out

Company Brief

ByteDance
Develops consumer internet and content platforms, including TikTok and other apps for short-form video, news, and entertainment. It also builds advertising, commerce, and creator tools that connect audiences, brands, and publishers across global markets.
Industry: Digital Media
Company Size: Enterprise (1,001+ employees)
Revenue: USD 1B+
Growth: Established Company
Headquarters: Beijing, China
Founded: 2012
WebsiteLinkedIn