intern in AI System Verification

Cadence Design Systems
France
Workplace: OnsiteInternshipFunction: Data Science & Machine LearningSkills: []

Develop a fully functional integration example combining PCIe Design IP (DIP) with PCIe Accelerated VIP (AVIP) to support customer bring-up and debugging. Build a unified virtual environment that connects a TLM-based virtual platform to RTL DIP via AXI AVIP bridges, execute PCIe enumeration via an OS/driver, and explore AI-assisted techniques for wrappers/glue logic, assertion generation, debuggability, and performance monitoring.

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Cadence Design Systems
Cadence Design Systems
22 hours ago

intern in AI System Verification

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Canonical indexed version, validated from employer's careers page.

Source: Company careers pageValidated by: Fursa AI
Last checked: 4 hours agoStatus: Live

Job Summary

Develop a fully functional integration example combining PCIe Design IP (DIP) with PCIe Accelerated VIP (AVIP) to support customer bring-up and debugging. Build a unified virtual environment that connects a TLM-based virtual platform to RTL DIP via AXI AVIP bridges, execute PCIe enumeration via an OS/driver, and explore AI-assisted techniques for wrappers/glue logic, assertion generation, debuggability, and performance monitoring.
Location: France
Workplace: Onsite
Employment Type: Internship
Job Function: Data Science & Machine Learning
Seniority: Intern level

Key Responsibilities

  • •Participate in developing a fully functional PCIe DIP + PCIe AVIP integration example to serve as a reference for customer bring-up.
  • •Use a TLM virtual platform on the bus/CPU side to program the PCIe controller and run an OS with a PCIe driver.
  • •Connect the TLM platform to the RTL DIP through AXI AVIP bridges and run RTL on Xcelium, Palladium, or Protium.
  • •Support PCIe enumeration so it executes on the operating system and discovers the PCIe AVIP endpoints.
  • •Explore AI-based techniques and extensions for debuggability, performance monitoring/analysis, and applicability to other high-speed protocols.

Key Requirements

Experience:Hardware verificationAI hardwarePCIeSimulationVirtual platforms
Tech Stack:PCIeAIAVIPVerification IPVIPDIPPalladiumProtiumXceliumTLMAXIAXI AVIP bridgesChipstackVerisium DebugAI debug assistantSystemVIPSPASystem Performance AnalyzerSystemVIP/SPA

Company Brief

Cadence Design Systems
Provides electronic design automation (EDA) software, IP, and services for semiconductor and systems companies to design, verify, and implement integrated circuits, systems-on-chip, and electronic systems across industries including communications, automotive, and consumer electronics.
Industry: Developer Tools
Company Size: Enterprise (1,001+ employees)
Revenue: USD 1B+
Growth: Public Company
Valuation: Public Company (Market Cap in USD)
Funding: IPO / Publicly Listed
Headquarters: San Jose, United States
Founded: 1988
Glassdoor
Glassdoor: 3.9
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