Design Engineering Manager

Cadence Design Systems
Bengaluru
Workplace: OnsiteFull timeFunction: Design (Product/UX/UI/Visual)Education: bachelorsSkills: ["Leadership","Mentorship","Communication","Teamwork","Problem-solving"]

Lead the Post Silicon Physical Layer Electrical Validation team in Bangalore, driving pre-silicon infrastructure development and post-silicon validation for Cadence's High Speed SERDES test chips. Design hardware/software test architectures, define rigorous test plans, automate tests with LabVIEW/Python, manage test reports, and mentor a small team to ensure high-quality validation outcomes across multiple protocols.

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Cadence Design Systems
Cadence Design Systems
6 months ago

Design Engineering Manager

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Source: Company careers pageValidated by: Fursa AI
Last checked: 3 hours agoStatus: Live

Job Summary

Lead the Post Silicon Physical Layer Electrical Validation team in Bangalore, driving pre-silicon infrastructure development and post-silicon validation for Cadence's High Speed SERDES test chips. Design hardware/software test architectures, define rigorous test plans, automate tests with LabVIEW/Python, manage test reports, and mentor a small team to ensure high-quality validation outcomes across multiple protocols.
Location: Bengaluru
Workplace: Onsite
Employment Type: Full time
Job Function: Design (Product/UX/UI/Visual)
Seniority: Manager level

Key Responsibilities

  • •Lead pre-silicon Physical Layer Electrical Validation infrastructure development and post-silicon validation efforts for Cadence’s High Speed SERDES test chips
  • •Design hardware and software architecture required to test the test chips (test PCBs, FPGA platforms, automation with LabVIEW/Python for HW control)
  • •Define test plans to rigorously test compliance of test chips to Physical Layer Electrical specifications
  • •Implement tests as planned and generate high-quality test reports based on results
  • •Mentor and manage a small validation team, including hiring and onboarding

Key Requirements

  • •6-10 years (with Btech) or 4-8 years (with Mtech) of experience in Post-Silicon Physical Layer Electrical Validation
  • •Deep Physical Layer electrical validation experience on at least one High speed SERDES protocol like PCIe, USB, DP, Ethernet, SRIO, JESD204, DDRIO
  • •Strong hands-on experience with lab equipment such as Oscilloscopes, Network Analyzer, Bit Error Rate Tester (BERT)
  • •Experience managing small teams (at least 2 members and above)
  • •1-2 years of experience in FPGA Design, PCB schematic and layout design & Prototyping
Experience:SemiconductorElectronicsHardwareTelecommunications
Education:Bachelor's
Skills:LeadershipMentorshipCommunicationTeamworkProblem-solving
Tech Stack:LabVIEWPythonC/C++VerilogRTLFPGATCLPCBLab equipmentOscilloscopeNetwork AnalyzerBERT

Company Brief

Cadence Design Systems
Provides electronic design automation (EDA) software, IP, and services for semiconductor and systems companies to design, verify, and implement integrated circuits, systems-on-chip, and electronic systems across industries including communications, automotive, and consumer electronics.
Industry: Developer Tools
Company Size: Enterprise (1,001+ employees)
Revenue: USD 1B+
Growth: Public Company
Valuation: Public Company (Market Cap in USD)
Funding: IPO / Publicly Listed
Headquarters: San Jose, United States
Founded: 1988
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