Sr. ASIC Design Verification Engineer (Silicon Engineering)

Develop and verify next-generation digital ASICs for Starlink’s space and ground infrastructure. Own block and system-level verification, including writing and reviewing test plans, building test harnesses, executing regressions, and closing code and functional coverage. Contribute to pre-silicon verification, chip bring-up, and post-silicon validation, using methodologies like UVM/OVM/VMM and constrained-random verification to ensure complex designs are fully validated.