Senior FPGA Verification Engineer

Anduril
Boulder
Workplace: OnsiteFull timeUSD 165,000 - 218,000Function: Hardware, Embedded & Systems EngineeringExperience: 8+ yearsEducation: bachelorsSkills: ["Technical leadership","Cross-functional collaboration","Planning","Status reporting"]

Help develop new imaging product lines by building and maturing FPGA/ASIC verification flows. Design verification environment architecture, create test plans and coverage metrics, and develop testbenches to verify RTL blocks using VHDL/SystemVerilog. Recommend improvements to continuous verification, support ASIC/FPGA lab validation, and provide technical leadership to verification teams through planning and status reporting across ground and flight testing.

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Anduril
Anduril
7 hours ago

Senior FPGA Verification Engineer

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Canonical indexed version, validated from employer's careers page.

Source: Company careers pageValidated by: Fursa AI
Last checked: 1 hour agoStatus: Live

Job Summary

Help develop new imaging product lines by building and maturing FPGA/ASIC verification flows. Design verification environment architecture, create test plans and coverage metrics, and develop testbenches to verify RTL blocks using VHDL/SystemVerilog. Recommend improvements to continuous verification, support ASIC/FPGA lab validation, and provide technical leadership to verification teams through planning and status reporting across ground and flight testing.
Location: Boulder
Workplace: Onsite
Employment Type: Full time
Job Function: Hardware, Embedded & Systems Engineering
Seniority: Mid level

Key Responsibilities

  • •Design and build verification environment architecture using SystemVerilog and/or OVM/UVM.
  • •Create written test plans and testcases, and track code and functional coverage.
  • •Develop testbenches to verify RTL blocks using VHDL and/or SystemVerilog.
  • •Recommend new tools and practices to improve the group’s ASIC/FPGA verification flow.
  • •Provide technical leadership for project verification teams by breaking down work, planning activities, and reporting status.

Pay and Benefits

Salary: USD 165,000 - 218,000
Equity and Bonus:Equity

Key Requirements

  • •A Bachelor’s in Electrical Engineering, Computer Engineering, or a related technical field is typically required.
  • •8+ years developing HDL firmware for FPGA devices.
  • •Demonstrated experience developing and simulating RTL designs using VHDL and/or Verilog in a professional FPGA or ASIC environment.
  • •Proven ability to design, implement, and execute verification testbenches for RTL blocks using VHDL and/or SystemVerilog.
  • •Experience applying chip-level verification methods (constrained-random testing, functional coverage, and assertion-based verification with SystemVerilog).
Experience:8+ yearsFPGAASICHDL firmware
Education:Bachelor's
Skills:Technical leadershipCross-functional collaborationPlanningStatus reporting
Languages:English
Tech Stack:SystemVerilogOVM/UVMVHDLRTLVerilogGitSubversionUnix/LinuxCC++PythonPerlShellQuestaSimSynplifyQuartusVivado

Eligibility

Security Clearance:Secret

Company Brief

Anduril
Designs and builds advanced defense systems combining autonomous aircraft, sensors, and AI-driven software for military and national security applications, focused on modernizing battlefield capabilities and distributed sensing.
Industry: Defense Technology
Company Size: Enterprise (1,001+ employees)
Growth: Scaleup
Valuation: Unicorn (USD 1B+)
Funding: Series E+
Headquarters: Costa Mesa, United States
Founded: 2017
WebsiteLinkedIn