Advanced Packaging SI/PI Engineer

Etched
San Jose
Workplace: OnsiteFull timeUSD 150,000 - 275,000 annuallyFunction: Software EngineeringExperience: 8+ yearsEducation: bachelorsSkills: ["Communication","Analytical","Problem-solving"]

Lead SI/PI analysis and optimization for high-power AI accelerator packaging across silicon, packages, and boards. Collaborate with ASIC PD/IP and packaging teams to push power delivery and high-speed signaling with OSAT/ODM partners, delivering robust PDN, C4/BGA pin strategies, and 112G/224G interposer routing within 2D/2.5D/3D packages.

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FursaFursa
Etched
Etched
3 months ago

Advanced Packaging SI/PI Engineer

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Source: Company careers pageValidated by: Fursa AI
Last checked: 7 hours agoStatus: Live

Job Summary

Lead SI/PI analysis and optimization for high-power AI accelerator packaging across silicon, packages, and boards. Collaborate with ASIC PD/IP and packaging teams to push power delivery and high-speed signaling with OSAT/ODM partners, delivering robust PDN, C4/BGA pin strategies, and 112G/224G interposer routing within 2D/2.5D/3D packages.
Location: San Jose
Workplace: Onsite
Employment Type: Full time
Job Function: Software Engineering

Key Responsibilities

  • •SI/PI analysis of designs and optimization within 2D/2.5D/3D packages.
  • •Close interaction with Package Layout Designers, ASIC PD and IP teams as well as Board Schematic/Layout/SI/PI teams to optimize the best electrical performance.
  • •Drive SI requirements into interposer/substrate layout (high-speed routing: 112G/224G) from preliminary design through tape-out.
  • •Drive PDN design and decoupling strategy across substrate and interposer, owning DC IR drop, dynamic IR drop, and impedance targets across all rails.
  • •Own ball map / C4 / BGA pin assignment from soft freeze through final freeze in partnership with package layout, ASIC PD, and board layout teams.

Pay and Benefits

Salary: USD 150,000 - 275,000 annually
Equity and Bonus:Equity
Perks:MedicalDentalVisionHousing SubsidyRelocationWellness StipendMeal Allowance

Key Requirements

  • •Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field with a strong understanding of signal integrity and power integrity concepts and fundamentals.
  • •8+ years of SI/PI experience on high-performance ASIC, processor, or accelerator platforms.
  • •Proven experience defining and closing PDN for high-power silicon, including substrate and PCB plane design, decap strategy, and dynamic IR/EM analysis.
  • •Experience with developing systems with high-speed interfaces like HBM, SerDes and D2D interfaces.
  • •Hands-on expertise with one or more of: ANSYS HFSS / SIwave, Cadence Sigrity (PowerSI / PowerDC), Keysight ADS.
Experience:8+ yearsSemiconductorsHardwareAI acceleratorSiliconPackaging
Education:Bachelor's
Skills:CommunicationAnalyticalProblem-solving
Tech Stack:ANSYS HFSSSIwaveCadence SigrityPowerSIPowerDCKeysight ADSHBMSerDesD2DCoWoSC4BGA2D2.5D3D

Company Brief

Etched
Designs transformer‑specialized AI inference ASICs (product: Sohu) to accelerate large‑language‑model workloads, working with TSMC for fabrication and targeting energy‑efficient inference performance.
Industry: Hardware Devices
Company Size: Medium (51 to 250 employees)
Growth: Early Stage Startup
Valuation: Unicorn (USD 1B+)
Funding: Series A
Headquarters: San Jose, United States
Founded: 2022
WebsiteLinkedInGlassdoor