Low Power Design Engineer (RTL)

AMD
Hyderabad
Workplace: OnsiteFull timeINR 3,338,160 - 4,768,800 annuallyFunction: Design (Product/UX/UI/Visual)Education: bachelorsSkills: ["Communication","Teamwork","Analytical thinking","Problem-solving","Willingness to learn"]

Plan, build, and integrate new and existing low-power features for AMD’s graphics processor IP, ensuring the final RTL design is bug-free. Own SoC/subsystem power architecture, develop power intent with UPF/CPF, and implement techniques like power/clock gating, multi-voltage domains, and DVFS. Use EDA tools to run and debug low-power checks, perform power estimation/optimization, and support low-power verification planning and execution.

Loading

Loading job details...

Preparing the role view and application actions.

FursaFursa
AMD
AMD
1 day ago

Low Power Design Engineer (RTL)

✓ Verified Job

Canonical indexed version, validated from employer's careers page.

Source: Company careers pageValidated by: Fursa AI
Last checked: 11 hours agoStatus: Live

Job Summary

Plan, build, and integrate new and existing low-power features for AMD’s graphics processor IP, ensuring the final RTL design is bug-free. Own SoC/subsystem power architecture, develop power intent with UPF/CPF, and implement techniques like power/clock gating, multi-voltage domains, and DVFS. Use EDA tools to run and debug low-power checks, perform power estimation/optimization, and support low-power verification planning and execution.
Location: Hyderabad
Workplace: Onsite
Employment Type: Full time
Job Function: Design (Product/UX/UI/Visual)

Key Responsibilities

  • •Define SoC and subsystem power architecture.
  • •Develop and maintain power intent using UPF/CPF methodologies.
  • •Implement low-power techniques including power gating, clock gating, multi-voltage domains, and DVFS.
  • •Collaborate with RTL designers to integrate low-power features and run/debug low-power checks using EDA tools.
  • •Perform power estimation, analysis, and optimization; drive power signoff and support low-power verification planning and execution.

Pay and Benefits

Salary: INR 3,338,160 - 4,768,800 annually

Key Requirements

  • •Strong knowledge of digital IC/SoC design flow and RTL design (Verilog/SystemVerilog).
  • •Expertise in UPF (Unified Power Format) and CPF (Common Power Format) with power-aware simulation and verification.
  • •Experience applying low-power design methodologies and implementing power intent for SoC/subsystem power architecture.
  • •Hands-on work with industry-standard EDA tools (Synopsys, Cadence, Siemens/Mentor) for low-power checks.
  • •Scripting/programming skills in Tcl, Perl/Python, and shell scripting.
Education:Bachelor's in Computer engineering/Electrical Engineering
Skills:CommunicationTeamworkAnalytical thinkingProblem-solvingWillingness to learn
Languages:En-us
Tech Stack:UPFCPFUPF/CPFVerilogSystemVerilogPower-aware simulationPower-aware verificationLow-power designPower gatingClock gatingMulti-voltage domainsDynamic Voltage and Frequency Scaling (DVFS)Retention and isolationStatic timingSynthesisImplementationPower estimationPower analysisSynopsysCadence

Company Brief

AMD
Designs and produces semiconductor products including CPUs, GPUs, and adaptive SoCs for consumer, enterprise, and embedded markets, competing across PCs, data centers, and gaming industries.
Industry: Electronics Manufacturing
Company Size: Enterprise (1,001+ employees)
Revenue: USD 1B+
Growth: Public Company
Valuation: Public Company (Market Cap in USD)
Funding: IPO / Publicly Listed
Headquarters: Santa Clara, United States
Founded: 1969
Glassdoor
Glassdoor: 3.9
WebsiteLinkedIn