ASIC Physical Design Technical Leader

Cisco
Vancouver
Workplace: HybridFull timeUSD 142,000 - 181,600 annuallyFunction: Design (Product/UX/UI/Visual)Experience: 8+ yearsEducation: bachelorsSkills: []

Own end-to-end ASIC physical design implementation for fullchip designs, from floorplanning and clock planning through RTL-to-GDSII signoff. Collaborate with system and package design teams, perform hierarchical implementation and physical verification, and optimize for performance, power, and die size. Improve tool flows and methodologies, ensure low-power design using UPF, and work with EDA, RTL/DFT, and foundry/standard-cell IP teams to deliver best-in-class physical design outcomes.

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FursaFursa
Cisco
Cisco
3 weeks ago

ASIC Physical Design Technical Leader

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Last checked: 14 hours agoStatus: Live

Job Summary

Own end-to-end ASIC physical design implementation for fullchip designs, from floorplanning and clock planning through RTL-to-GDSII signoff. Collaborate with system and package design teams, perform hierarchical implementation and physical verification, and optimize for performance, power, and die size. Improve tool flows and methodologies, ensure low-power design using UPF, and work with EDA, RTL/DFT, and foundry/standard-cell IP teams to deliver best-in-class physical design outcomes.
Location: Vancouver
Workplace: Hybrid
Employment Type: Full time
Job Function: Design (Product/UX/UI/Visual)

Key Responsibilities

  • •Drive fullchip floorplanning by understanding design architecture, foundry integration guidelines, and IP placement constraints.
  • •Collaborate with system and package design teams and incorporate requirements into the fullchip floorplan.
  • •Perform hierarchical implementation flow including partitioning, pin assignment, clock planning, and bump planning, using Fullchip clock mesh and Flex-HTree methods.
  • •Lead RTL-to-GDSII implementation (floorplan, power grid plan, place and route) with static timing analysis, power integrity, physical verification, and equivalence checks to optimize performance, power, and die size.
  • •Analyze and improve tool flows and methodologies; partner with RTL, DFT, implementation, EDA vendors, and foundry/standard-cell IP teams to enable best-in-class design methodology.

Pay and Benefits

Salary: USD 142,000 - 181,600 annually
Equity and Bonus:Equity
Perks:Health InsuranceDentalVision401kParental LeaveDisability CoverageLife InsurancePaid Holidays

Key Requirements

  • •Bachelor’s degree in Electrical Engineering with 8+ years of physical design experience, or Master’s degree with 6+ years, or PhD with 3+ years.
  • •Experience with fullchip physical design activities.
  • •Experience with RTL-to-GDSII flow and design tapeouts in 7nnm/5nm/3nm or below.
  • •Experience with EDA tools such as Innovus, Tempus/Primetime, Redhawk/Voltus, or Calibre/Pegasus.
  • •Proficiency in hierarchical implementation and physical design convergence with focus on timing, power, and verification.
Experience:8+ yearsPhysical designRTL-to-GDSIIASIC
Education:Bachelor's in Electrical Engineering
Tech Stack:InnovusTempus/PrimetimeRedhawk/VoltusCalibre/PegasusRTL-to-GDSIIStatic timing analysisPower integrityUPFPythonFullchip clock meshFlex-HTreeFullchip floorplanningPlace and route

Company Brief

Cisco
Global technology company that designs, manufactures, and sells networking hardware, telecommunications equipment, and high-technology services and products for enterprises, service providers, and governments worldwide.
Industry: Networking Equipment
Company Size: Enterprise (1,001+ employees)
Revenue: USD 1B+
Growth: Public Company
Valuation: Public Company (Market Cap in USD)
Funding: IPO / Publicly Listed
Headquarters: San Jose, United States
Founded: 1984
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