CPU Architecture and RTL Design Engineer

AMD
Dublin
Workplace: HybridFull timeEUR 58,380 - 83,400 annuallyFunction: Architecture & Urban PlanningEducation: bachelorsSkills: ["Critical thinking","Creativity","Communication","Collaboration","Continuous learning"]

Design and implement CPL (Chip Pervasive Logic) CPU microarchitecture for next-generation caches and cores, driving clocking, reset, and power integration from concept through tapeout. Contribute to design closure using static timing, CDC/gate CDC, and static power analysis, collaborating across logic design, physical design, and verification. Help address customer challenges with AMD’s value proposition while improving high-frequency performance and power efficiency across server, desktop, and laptop CPUs.

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AMD
AMD
1 day ago

CPU Architecture and RTL Design Engineer

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Last checked: 9 hours agoStatus: Live

Job Summary

Design and implement CPL (Chip Pervasive Logic) CPU microarchitecture for next-generation caches and cores, driving clocking, reset, and power integration from concept through tapeout. Contribute to design closure using static timing, CDC/gate CDC, and static power analysis, collaborating across logic design, physical design, and verification. Help address customer challenges with AMD’s value proposition while improving high-frequency performance and power efficiency across server, desktop, and laptop CPUs.
Location: Dublin
Workplace: Hybrid
Employment Type: Full time
Job Function: Architecture & Urban Planning

Key Responsibilities

  • •Define and implement CPL microarchitecture for AMD CPUs, focusing on clocking, reset, and power in next-generation caches/core.
  • •Deliver RTL designs reliably from concept through tapeout under complex requirements.
  • •Drive design closure using Static Timing, CDC/Gate CDC, and Static Power analysis.
  • •Identify customer challenges and help insert AMD value proposition to address them.
  • •Contribute technical innovations enabling high-performance, high-frequency, and power-efficient caches, fabrics, and interfaces across CPUs.

Pay and Benefits

Salary: EUR 58,380 - 83,400 annually

Key Requirements

  • •Proficiency with Verilog HDL and Clock/Power Domain Crossing concepts.
  • •Understanding of modern CPU architecture, including experience designing shared cache or last level cache and related IPs (preferred).
  • •Drive design closure using Static Timing, CDC/Gate CDC, and Static Power analysis.
  • •Collaborate effectively across logic design, physical design, and verification teams to deliver designs.
  • •Bachelors or Masters degree in computer engineering or Electrical Engineering.
Experience:HardwareSemiconductorCPU architectureRTL design
Education:Bachelor's in Computer Engineering / Electrical Engineering
Skills:Critical thinkingCreativityCommunicationCollaborationContinuous learning
Languages:English
Tech Stack:Verilog HDLStatic TimingCDCGate CDCStatic Power analysis

Company Brief

AMD
Designs and produces semiconductor products including CPUs, GPUs, and adaptive SoCs for consumer, enterprise, and embedded markets, competing across PCs, data centers, and gaming industries.
Industry: Electronics Manufacturing
Company Size: Enterprise (1,001+ employees)
Revenue: USD 1B+
Growth: Public Company
Valuation: Public Company (Market Cap in USD)
Funding: IPO / Publicly Listed
Headquarters: Santa Clara, United States
Founded: 1969
Glassdoor
Glassdoor: 3.9
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