Package Development Engineer -Singapore

Work with the Silicon Platform team to deliver chip packaging design solutions end-to-end, from packaging selection and implementation to PinMap definition and board-level interconnection. Tackle signal integrity (SI) and power integrity (PI) analysis and optimization for complex SoC chips, including high-speed interfaces like DDR, PCIe, and Serdes. Partner with chip and board-level designers to resolve interface issues and support R&D progress through tape-out and mass production readiness.