Custom SOC IP Verification Engineer

NVIDIA
Santa Clara, Austin
Workplace: OnsiteFull timeUSD 168,000 - 310,500 annuallyFunction: Hardware, Embedded & Systems EngineeringExperience: 8+ yearsEducation: mastersSkills: ["Collaboration"]

Verify next-generation custom SoC and IP solutions, focusing on fabric and interconnect correctness, performance, and compliance from IP bring-up through full chip integration. Own ASIC verification activities including DMA, routing, arbitration, ordering, flow control, and protocol compliance. Create UVM-based test plans and constrained-random/directed SystemVerilog testbenches for NoC topologies and multi-agent integrations, and collaborate across architecture, SW/FW, design, modeling, emulation, and post-silicon teams.

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FursaFursa
NVIDIA
NVIDIA
2 hours ago

Custom SOC IP Verification Engineer

✓ Verified Job

Canonical indexed version, validated from employer's careers page.

Source: Company careers pageValidated by: Fursa AI
Last checked: 2 hours agoStatus: Live
Reposted: similar role first listed 7 months ago

Job Summary

Verify next-generation custom SoC and IP solutions, focusing on fabric and interconnect correctness, performance, and compliance from IP bring-up through full chip integration. Own ASIC verification activities including DMA, routing, arbitration, ordering, flow control, and protocol compliance. Create UVM-based test plans and constrained-random/directed SystemVerilog testbenches for NoC topologies and multi-agent integrations, and collaborate across architecture, SW/FW, design, modeling, emulation, and post-silicon teams.
Location: Santa Clara, Austin
Workplace: Onsite
Employment Type: Full time
Job Function: Hardware, Embedded & Systems Engineering
Seniority: Mid level

Key Responsibilities

  • •Perform ASIC design verification for fabric and interconnect IP blocks and full chip integration, including DMA, routing, arbitration, ordering, flow control, and protocol compliance.
  • •Develop and implement UVM-based test plans for fabric and interconnect verification across IP-level and system-level scenarios.
  • •Design and implement constrained-random and directed SystemVerilog testbenches for interconnect fabrics, NoC topologies, and multi-agent SoC integrations.
  • •Collaborate with architecture, SW/FW, design, modeling, emulation, and post-silicon validation teams to deliver first-time-right verification plans and execution.
  • •Drive silicon and platform verification strategies and methodologies for fabric and interconnect subsystems.

Pay and Benefits

Salary: USD 168,000 - 310,500 annually
Equity and Bonus:Equity

Key Requirements

  • •B.S. or M.S. degree in Computer Engineering, Electrical Engineering, or a related field (or equivalent experience).
  • •8+ years of experience in ASIC verification with a focus on fabric, interconnect, or NoC verification at IP and full chip levels.
  • •Strong knowledge of SystemVerilog and UVM methodology.
  • •Hands-on experience with interconnect and bus protocols (e.g., AMBA AXI, CHI) including ordering, coherency, and flow control semantics.
  • •Familiarity with SoC architectures, NoC topologies, and multi-initiator/multi-target interconnect designs.
Experience:8+ yearsASIC verificationSoCFabric verificationInterconnect verificationNetwork-on-chip
Education:Master's
Skills:Collaboration
Tech Stack:SystemVerilogUVMPythonPerlTCLAMBA AXICHISVAConstrained-randomDirected testbenchesPalladiumVeloceEmulation

Company Brief

NVIDIA
Designs and manufactures GPUs, AI accelerators, and system-on-chip products for gaming, data centers, professional visualization, and automotive markets, enabling advanced graphics, AI, and high-performance computing solutions worldwide.
Industry: Electronics Manufacturing
Company Size: Enterprise (1,001+ employees)
Revenue: USD 1B+
Growth: Public Company
Valuation: Public Company (Market Cap in USD)
Funding: IPO / Publicly Listed
Headquarters: Santa Clara, United States
Founded: 1993
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