Physical Design Lead with STA

AMD
Hyderabad
Full timeINR 3,338,160 - 4,768,800 annuallyFunction: Design (Product/UX/UI/Visual)Experience: 8+ yearsEducation: mastersSkills: ["Collaboration","Communication","Self-driving","Organization","Automation affinity"]

Own SubSystem physical design signoff closure for SoC partitions (including high frequency CPU, HBM, DDR, and SerDes interfaces), driving RTL-to-GDS execution toward first-pass silicon success. Lead PnR execution and closure, converge synthesis-to-route, and deliver signoff on STA, EMIR, and PV. Collaborate across geographies with design teams, methodology, and CAD teams, improve closure with automation/dashboarding, and use deep STA/route/CTS expertise to resolve critical issues.

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FursaFursa
AMD
AMD
23 hours ago

Physical Design Lead with STA

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Last checked: 1 hour agoStatus: Live

Job Summary

Own SubSystem physical design signoff closure for SoC partitions (including high frequency CPU, HBM, DDR, and SerDes interfaces), driving RTL-to-GDS execution toward first-pass silicon success. Lead PnR execution and closure, converge synthesis-to-route, and deliver signoff on STA, EMIR, and PV. Collaborate across geographies with design teams, methodology, and CAD teams, improve closure with automation/dashboarding, and use deep STA/route/CTS expertise to resolve critical issues.
Location: Hyderabad
Employment Type: Full time
Job Function: Design (Product/UX/UI/Visual)

Key Responsibilities

  • •Own SS partitions PnR execution and closure, including SS SoC SS PD closure.
  • •Drive improvements in closure and analyze data/feedback to the design team.
  • •Work with PnR team members for closure convergence from synthesis to route.
  • •Provide closure signoff on STA, EMIR, and PV, and collaborate with CAD and central methodology.
  • •Develop automation to refine and improve design signoff requirements and dashboarding.

Pay and Benefits

Salary: INR 3,338,160 - 4,768,800 annually

Key Requirements

  • •8+ years of experience in design signoff closure.
  • •Strong PnR background with critical problem-solving to improve PPA and debug.
  • •Technical depth in CTS, Route, and STA, including SDC coding and debug skills.
  • •Experience with EMIR-driven power grid knowledge and PnR/STA signoff correlation and convergence.
  • •Strong scripting experience (TCL, Perl, Python, Makefile).
Experience:8+ yearsSoC physical designSTAPnRE2E design flow
Education:Master's in Computer Engineering / Electrical Engineering
Skills:CollaborationCommunicationSelf-drivingOrganizationAutomation affinity
Languages:En-us
Tech Stack:RTLGDSSoCPnRSTAEMIRPVCTSRouteSDCTCLPerlPythonMakefileSynopsysCadenceMentorDashboardingTiming closurePhysical verification

Company Brief

AMD
Designs and produces semiconductor products including CPUs, GPUs, and adaptive SoCs for consumer, enterprise, and embedded markets, competing across PCs, data centers, and gaming industries.
Industry: Electronics Manufacturing
Company Size: Enterprise (1,001+ employees)
Revenue: USD 1B+
Growth: Public Company
Valuation: Public Company (Market Cap in USD)
Funding: IPO / Publicly Listed
Headquarters: Santa Clara, United States
Founded: 1969
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Glassdoor: 3.9
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