Full chip Physical verification Engineer

AMD
Hyderabad
Full timeINR 3,338,160 - 4,768,800 annuallyFunction: QA, Test & Release EngineeringExperience: 9+ yearsEducation: bachelorsSkills: ["Teamwork","Communication","Problem-solving"]

Lead full chip integration and physical verification for FPGA/SoC designs, with a focus on reducing human error through automation. Improve integration flow efficiency using EDA features, and collaborate with CAD/SiTech/PKG/PD and EDA vendors to integrate IPs for on-time tapeout. Debug full-chip LVS/DRC/Antenna issues, update rule files for faster turnaround, and support RDL development for advanced packaging and monolithic technologies.

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FursaFursa
AMD
AMD
2 days ago

Full chip Physical verification Engineer

✓ Verified Job

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Source: Company careers pageValidated by: Fursa AI
Last checked: 15 hours agoStatus: Live

Job Summary

Lead full chip integration and physical verification for FPGA/SoC designs, with a focus on reducing human error through automation. Improve integration flow efficiency using EDA features, and collaborate with CAD/SiTech/PKG/PD and EDA vendors to integrate IPs for on-time tapeout. Debug full-chip LVS/DRC/Antenna issues, update rule files for faster turnaround, and support RDL development for advanced packaging and monolithic technologies.
Location: Hyderabad
Employment Type: Full time
Job Function: QA, Test & Release Engineering
Seniority: Mid level

Key Responsibilities

  • •Drive full chip integration and physical verification of FPGA/SoC designs.
  • •Develop SoC RDL for monolithic and advanced package technologies.
  • •Collaborate with PD, CAD, SiTech, EMIR, PKG, and EDA vendors to integrate IPs for on-time tapeout.
  • •Automate integration flows to improve functional efficiency and reduce human error.
  • •Debug full chip LVS/DRC/Antenna issues and update rule files for faster resolution using a multi-point approach.

Pay and Benefits

Salary: INR 3,338,160 - 4,768,800 annually

Key Requirements

  • •Master’s/Bachelor’s degree in Electrical/Electronic engineering with 9+ years of experience in FPGA/SoC full chip physical verification and PDK updates.
  • •Experience with RDL, bump, and ubump development for full chip physical verification.
  • •Strong scripting skills in PERL, TCL, and Python.
  • •Ability to debug full chip LVS/DRC/Antenna issues and modify rule files to speed up debug.
  • •Sound knowledge of FinFET technology DRC debugging and fixes, including parasitic extraction and physical verification checks.
Experience:9+ yearsFPGASoCFull chip verificationEDAPhysical verificationFinFET
Education:Bachelor's in Electrical/Electronic engineering
Skills:TeamworkCommunicationProblem-solving
Tech Stack:FPGASoCPhysical verificationLVSDRCAntennaFinFETPDKRDLBumpUbumpAoASSITAoA/SSITParasitic extractionPERLTCLPythonSKILLEDA

Company Brief

AMD
Designs and produces semiconductor products including CPUs, GPUs, and adaptive SoCs for consumer, enterprise, and embedded markets, competing across PCs, data centers, and gaming industries.
Industry: Electronics Manufacturing
Company Size: Enterprise (1,001+ employees)
Revenue: USD 1B+
Growth: Public Company
Valuation: Public Company (Market Cap in USD)
Funding: IPO / Publicly Listed
Headquarters: Santa Clara, United States
Founded: 1969
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Glassdoor: 3.9
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