Olix

1 month ago

Senior Mixed-Signal Verification Engineer

✓ Verified Job

Canonical indexed version, validated from employer's careers page.

Source: Company careers pageValidated by: Fursa AI

Last checked: 6 hours agoStatus: Live

Job Summary

Senior Mixed-Signal Verification Engineer responsible for verification of analog and mixed-signal blocks across high-speed IO chains, building models, environments, and testbenches to detect silicon bugs before tape-out, and driving AMS co-simulation and coverage from block to top-level.

Location: Austin

Workplace: Onsite

Employment Type: Full time

Job Function: Solutions Engineering & Sales Engineering

Seniority: Manager level

Key Responsibilities

•Own the verification strategy and test plan for our mixed-signal subsystems, from block level through subsystem and top-level integration.
•Define the modeling approach and fidelity tiers - decide what gets a real-number model, what needs Verilog-AMS, and where transistor-level co-sim is required - and document the accuracy/runtime trade-offs.
•Develop and validate analog behavioral models against transistor-level references, owning the model-vs-schematic equivalence checks that keep the abstraction honest.
•Build self-checking testbenches and reusable verification components for analog/digital interactions: CDR lock, adaptation and calibration loop convergence, mode and power-state transitions, clock dividers, deserializers, and clock-domain crossings.
•Drive AMS co-simulation flows (Spice/FastSpice coupled with digital simulators) and own their setup, performance, and runtime trade-offs.

Pay and Benefits

Salary: USD 264,000 annually

Equity and Bonus:Equity

Key Requirements

•BS/MS in Electrical Engineering or related field with 5+ years of analog/mixed-signal verification experience on complex SoCs or mixed-signal IP.
•Hands-on expertise with AMS modeling and verification: Verilog-AMS and real-number modeling (SystemVerilog real / wreal), and analog-digital co-simulation flows (e.g., Spectre AMS, FastSpice coupled with a digital simulator).
•Proficiency in SystemVerilog, with solid assertion-based verification skills and the ability to architect self-checking testbenches and reusable verification components.
•Demonstrated ability to model analog blocks at the appropriate level of abstraction and to validate those models against transistor-level references.
•Strong debug skills across the analog/digital boundary, with a structured approach to test planning, functional coverage, and closure.

Experience:5+ yearsSemiconductorsHardwareSoCAI hardware

Education:Bachelor's

Skills:Verilog-AMSSystemVerilogSpectre AMSFastSpicePythonTCLMakeAssertion-based verificationTestbenchesAMS co-simulation

Languages:English

Tech Stack:Verilog-AMSSystemVerilogSpectre AMSFastSpiceVerilogAMSCo-simulationPythonTCLMake

Company Brief

Olix

Olix designs and manufactures optical processors (Optical Tensor Processing Units) for training and running inference on large AI models, aiming to deliver higher performance and lower energy consumption than conventional silicon-based accelerators.

Industry: Deep Tech

Company Size: Medium (51 to 250 employees)

Growth: Early Stage Startup

Headquarters: London, United Kingdom

Founded: 2024

Glassdoor: 3.0

Website LinkedIn Glassdoor

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Olix

1 month ago

Senior Mixed-Signal Verification Engineer

✓ Verified Job

Canonical indexed version, validated from employer's careers page.

Source: Company careers pageValidated by: Fursa AI

Last checked: 6 hours agoStatus: Live

Job Summary

Location: Austin

Workplace: Onsite

Employment Type: Full time

Job Function: Solutions Engineering & Sales Engineering

Seniority: Manager level

Key Responsibilities

•Own the verification strategy and test plan for our mixed-signal subsystems, from block level through subsystem and top-level integration.
•Define the modeling approach and fidelity tiers - decide what gets a real-number model, what needs Verilog-AMS, and where transistor-level co-sim is required - and document the accuracy/runtime trade-offs.
•Develop and validate analog behavioral models against transistor-level references, owning the model-vs-schematic equivalence checks that keep the abstraction honest.
•Build self-checking testbenches and reusable verification components for analog/digital interactions: CDR lock, adaptation and calibration loop convergence, mode and power-state transitions, clock dividers, deserializers, and clock-domain crossings.
•Drive AMS co-simulation flows (Spice/FastSpice coupled with digital simulators) and own their setup, performance, and runtime trade-offs.

Pay and Benefits

Salary: USD 264,000 annually

Equity and Bonus:Equity

Key Requirements

•BS/MS in Electrical Engineering or related field with 5+ years of analog/mixed-signal verification experience on complex SoCs or mixed-signal IP.
•Hands-on expertise with AMS modeling and verification: Verilog-AMS and real-number modeling (SystemVerilog real / wreal), and analog-digital co-simulation flows (e.g., Spectre AMS, FastSpice coupled with a digital simulator).
•Proficiency in SystemVerilog, with solid assertion-based verification skills and the ability to architect self-checking testbenches and reusable verification components.
•Demonstrated ability to model analog blocks at the appropriate level of abstraction and to validate those models against transistor-level references.
•Strong debug skills across the analog/digital boundary, with a structured approach to test planning, functional coverage, and closure.

Experience:5+ yearsSemiconductorsHardwareSoCAI hardware

Education:Bachelor's

Skills:Verilog-AMSSystemVerilogSpectre AMSFastSpicePythonTCLMakeAssertion-based verificationTestbenchesAMS co-simulation

Languages:English

Tech Stack:Verilog-AMSSystemVerilogSpectre AMSFastSpiceVerilogAMSCo-simulationPythonTCLMake

Company Brief

Olix

Industry: Deep Tech

Company Size: Medium (51 to 250 employees)

Growth: Early Stage Startup

Headquarters: London, United Kingdom

Founded: 2024

Glassdoor: 3.0

Website LinkedIn Glassdoor